Semiconductor device and method of manufacturing the same

ABSTRACT

A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode. A second semiconductor layer of a first conductivity type serving as a drain region is provided on the channel semiconductor layer.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to semiconductor devices,and more particularly, to a vertical surround gate metal-oxidesemiconductor field-effect transistor (hereinafter referred to as“MOSFET”). The present invention further relates to a dynamic randomaccess memory, an inverter circuit, and a static random access memoryusing such a vertical surround gate MOSFET. The present invention alsorelates to a method of manufacturing such a semiconductor device.

[0003] 2. Description of the Background Art

[0004]FIG. 101 is a schematic diagram of a conventional planar typeMOSFET. Referring to FIG. 101, a gate electrode 3 is provided on aP-type silicon substrate 1 with a gate insulating film 4 interposedtherebetween. N-type source/drain regions 6 a, 6 b are provided on bothsides of gate electrode 3 in the main surface of silicon substrate 1.

[0005] Operation will now be described. When a positive potential isapplied to gate electrode 3, the following reaction occurs in the mainsurface of silicon substrate 1

B→B⁻+h⁺

[0006] where B is boron, B⁻ is a boron anion, and h⁺ is a hole.

[0007] More specifically, when a positive potential is applied to gateelectrode 3, boron is separated into boron anions and holes. Boronanions are attracted to gate electrode 3. On the other hand, holesrepulse gate electrode 3 to escape in silicon substrate 1, which in turngenerates a depletion layer 17 in the main surface of a channel regionof silicon substrate 1. Depletion layer 17 is a region where neitherelectrons nor holes exist, that is, where no carriers serving to make acurrent flow exist.

[0008] As a positive potential applied to gate electrode 3 is increased,depletion layer 17 is enlarged and its width Wd is increased. However,increase of the width Wd of depletion layer 17 is limited. The width ofdepletion layer 17 is determined by an impurity concentration. Thelarger the impurity concentration, the narrower the width Wd of thedepletion layer. The smaller the impurity concentration, the wider thewidth Wd. The maximum value of the width Wd of depletion layer 17 iscalled maximum depletion layer width.

[0009] When the width Wd of depletion layer 17 reaches the maximumdepletion layer width, an inversion layer 18 is formed on the surface ofthe channel region, rendering source 6 a/drain 6 b conductive.

[0010] When integration density of a semiconductor device is increased,an area occupied by the MOSFET needs to be small.

[0011]FIG. 102 is a perspective view extracting and illustrating mainportions of the conventional vertical type surround gate MOSFET improvedso that an area occupied by the MOSFET may be made small.

[0012] Referring to FIG. 2, gate electrode 3 surrounds a plug-shapedsilicon 5 with gate insulating film 4 interposed therebetween. Sourceregion 6 a is provided at an upper end of plug-shaped silicon 5, anddrain region 6 b is provided at a lower end thereof. Drain region 6 b isformed in the main surface of the silicon substrate.

[0013] Aluminum interconnections 10 a, 10 b, and 10 c are connected tosource region 6 a, gate electrode 3, and drain region 6 b, respectively.

[0014] When a positive potential is applied to gate electrode 3, aninversion layer is generated on the sidewall surface of the plug-shapedsilicon, causing a current to flow from source region 6 a to drainregion 6 b. In other words, the current flows in the directionperpendicular to the silicon substrate.

[0015] Comparison is now made between an area occupied by the planartype MOSFET and an area occupied by the vertical type surround gateMOSFET.

[0016] Let L be a gate length of the planar type MOSFET, and W be achannel width of the planar type MOSFET, referring to FIG. 101, anoccupied area Splanar of the channel region is

Splanar=L·W

[0017] On the other hand, in the case of the vertical type surround gateMOSFET, referring to FIG. 103 (which is a simplification of FIG. 102),when the radius of the channel region is R, the channel width W is 2πR.An occupied area of the channel region is

Svertical=πR ² =W ²/4π

[0018] Therefore, when transistors having the gate length L equal to thechannel width W are formed of a planar type MOSFET and a vertical typesurround gate MOSFET, respectively, the ratio of respective occupiedareas is

Svertical/Splanar=1/4π

[0019] More specifically, an occupied area of the vertical type surroundgate MOSFET is 1/12 or less of that of the planar type MOSFET.

[0020] If occupied areas of both the vertical type surround gate MOSFETand the planar type MOSFET are made equal, it is possible to increase win the vertical type surround gate MOSFET. This is a first advantage ofthe vertical type surround gate MOSFET.

[0021] Referring to FIGS. 102 and 103, in the vertical type surroundgate MOSFET, it is possible to deplete the entire channel by decreasingthe radius of channel plug 5. Therefore, the vertical type surround gateMOSFET has advantages the same as those of a conventional SOI(Silicon-On-Insulator) MOSFET. Detailed description thereof will begiven hereinafter.

[0022] If the entire channel can be depleted, it is possible to suppressa subthreshold current (a leakage current in a weakly inverted state),which in turn improves a circuit characteristic.

[0023] A subthreshold coefficient S is expressed by the followingexpression:

S=ln10·kT/q·(1+Cd/Cox)

[0024] where k is a Boltzmann constant, T is an absolute temperature, qis an elementary electric charge, Cd is a depletion layer capacitance ofthe MOSFET, and Cox is a gate insulating film capacitance.

[0025] As is clear from the above equation, when Cd=0 holds, thesubthreshold coefficient S takes the minimum value (ln10·kT/q=60mV/dec).

[0026]FIG. 104 is a cross-sectional view of an SOIMOSFET. An SIO layer15 is formed on a buried oxide film 16. Gate electrode 3 is formed onSOI layer 15 with gate insulating film 4 interposed therebetween.Source/drain regions 6 a, 6 b are formed on both sides of gate electrode3 in the surface of SOI layer 15. In the figure, Wd is a depletion layerwidth, t_(SOI) is the film thickness of SOI layer 15, and t_(BOX) is thefilm thickness of buried oxide film 16.

[0027] When the entire SOI layer 15 is not depleted (that is, whenWd<t_(SOI) holds), the depletion layer capacitance Cd of the SOIMOSFETis, similar to the case of the MOSFET shown in FIG. 101, expressed bythe following equation:

Cd=ε _(gi) /Wd

[0028] On the other hand, when the film thickness of buried oxide film16 is sufficiently larger than that of SOI layer 15 (t_(BOX)>>t_(SOI)),and the entire SOI layer 15 is depleted (when it is in a fully depletedstate, Wd≧t_(SOI)), the depletion layer capacitance Cd is substantially0. In the case of the SOIMOSFET, it is possible to make the depletionlayer capacitance Cd zero by adjusting the film thickness of SOI layer15, thereby suppressing a subthreshold current.

[0029] The above-described advantage of the SOIMOSFET can be implementedin the vertical type surround gate MOSFET. More specifically, when thefully depleted state is implemented in the vertical type surround gateMOSFET, the depletion layer capacitance Cd is 0 similar to the case ofthe SOIMOSFET. Since electric power lines extend in the radialdirection, the phenomenon of which is unique to the surround typeMOSFET, the depletion layer capacitance Cd is smaller than that of theMOSFET shown in FIG. 101 even in the state of incomplete depletion.

[0030] The following equation shows the relation between the radius Rand the depletion layer capacitance Cd of the vertical type surroundgate MOSFET, and FIG. 105 shows the equation in the form of graph.${Cd} = \frac{ɛ_{Si}}{R \cdot {\ln \left( {R/\left( {R - {Wd}} \right)} \right)}}$

[0031] When R/Wd<1 holds, complete depletion of the channel can beimplemented. Therefore, the depletion layer capacitance Cd is 0. Even ifR/Wd>1 holds, the depletion layer capacitance Cd is smaller than that ofa bulk MOSFET shown in FIG. 100.

[0032] As described above, in the vertical type surround gate MOSFET, itis possible to make the depletion layer capacitance Cd zero by adjustingthe radius of channel plug 5, which in turn makes it possible tosuppress the subthreshold current. As a result, the vertical typesurround gate MOSFET has a second advantage of improving a circuitcharacteristic.

[0033] A third advantage of the vertical type surround gate MOSFET isthat the entire channel plug can be made an inversion layer, therebyincreasing a drain current.

[0034] As described above, the vertical type surround gate MOSFET hasthree advantages.

[0035] FIGS. 106 to 109 are partial cross-sectional views of asemiconductor device in respective steps of the manufacturing process ofthe conventional vertical type surround gate MOSFET.

[0036] Referring to FIG. 106, plug-shaped silicon 5 of the vertical typesurround gate MOSFET is formed by anisotropically etching substrate 1.Plug-shaped silicon 5 is cylindrical when represented in a perspectiveview as shown in FIG. 111.

[0037] Referring to FIG. 107, gate insulating film 4 is deposited onsubstrate 1 so as to cover plug-shaped silicon 5. Then, impurity ionsare implanted into the surface of substrate 1 through gate insulatingfilm 4 to form source region 6 a and drain region 6 b.

[0038] Referring to FIG. 108, polysilicon 3 serving as a gate electrodeis deposited on substrate 1.

[0039] Referring to FIGS. 108 and 109, polysilicon 3 is selectivelyetched to form gate electrode 3.

[0040] Referring to FIG. 110, an interlayer insulating film 2 isdeposited on substrate 1 so as to cover gate electrode 3. A contact holefor exposing the surface of source region 6 a, a contact hole forexposing a part of the surface of gate electrode 3, and a contact holefor exposing a part of the surface of drain region 6 b are formed ininterlayer insulating film 2. By connecting aluminum interconnections 10a, 10 b, 10 c to respective portions through these contact holes, thevertical type surround gate MOSFET shown in FIG. 102 is completed.

[0041] Although the conventional vertical type surround gate MOSFET hadthree advantages as described above, it also had the following problems.

[0042] Referring to FIG. 102, the diameter of plug-shaped silicon 5 mustbe made larger than a contact hole 8 a so that aluminum interconnection10 a connected to drain region 6 a and gate electrode 3 might not beshort-circuited. Formation of large plug-shaped silicon 5 causes an areaoccupied by the device to increase. Formation of large plug-shapedsilicon 5 also causes the channel plug not to be depleted completely,resulting in no inversion of the entire channel plug. Therefore, theconventional vertical type surround gate MOSFET was not able to fullyenjoy the above-described three advantages.

SUMMARY OF THE INVENTION

[0043] One object of the present invention is to provide a verticalsurround gate MOSFET improved so that an area occupied by the device canbe substantially decreased.

[0044] Another object of the present invention is to provide a verticaltype surround gate MOSFET improved so that a subthreshold current can besubstantially suppressed, and that a circuit characteristic can besufficiently enhanced.

[0045] Still another object of the present invention is to provide avertical type surround gate MOSFET improved so that the entire channelportion can be made an inversion layer, and that a drain current can besubstantially increased.

[0046] A further object of the present invention is to provide a dynamicrandom access memory using such a vertical type surround gate MOSFET.

[0047] A further object of the present invention is to provide aninverter circuit using such a vertical type surround gate MOSFET.

[0048] A further object of the present invention is to provide a staticrandom access memory using such a vertical type surround gate MOSFET.

[0049] A further object of the present invention is to provide a methodof manufacturing such a vertical type surround gate MOSFET.

[0050] According to a first aspect of the present invention, asemiconductor device controls a flow of majority carriers by a voltageapplied to the gate. The semiconductor device includes a substratehaving a main surface. A first conductive layer of a first conductivitytype serving as one source/drain region is provided in the main surfaceof the substrate. A first interlayer insulating film is provided on thesubstrate. A gate electrode having an upper surface and a lower surfaceis provided on the first interlayer insulating film. A second interlayerinsulating film is provided on the first interlayer insulating films soas to cover the gate electrode. A contact hole for exposing a part ofthe surface of the first conductive layer is provided so as to penetratethrough the first interlayer insulating film, the gate electrode, andthe second interlayer insulating film. A sidewall surface of the contacthole is covered with a gate insulating film. A first semiconductor layerof a first conductivity type is formed on the surface of the firstconductive layer in contact therewith up to the lower surface of thegate electrode in the contact hole. A channel semiconductor layer isformed on the surface of the first semiconductor layer in contacttherewith up to the upper surface of the gate electrode in the contacthole. A second semiconductor layer of a first conductivity type servingas the other source/drain region is provided on the surface of thechannel semiconductor layer in contact therewith.

[0051] According to a second aspect of the present invention, asemiconductor device controls a flow of majority carriers by a voltageapplied to the gate. The semiconductor device includes a substratehaving a main surface. A first conductive layer of a first conductivitytype serving as one source/drain region is provided in the main surfaceof the substrate. A first interlayer insulating film is provided on thesubstrate. A gate electrode having an upper surface and a lower surfaceis provided on the first interlayer insulating film. A second interlayerinsulating film is provided on the first interlayer insulating film soas to cover the gate electrode. A contact hole for exposing a part ofthe surface of the first conductive layer is provided so as to penetratethrough the first interlayer insulating film, the gate electrode, andthe second interlayer insulating film. A sidewall surface of the contacthole is covered with a gate insulating film. A silicon thin film havinga recessed portion in a portion of the contact hole is provided incontact with the first conductive layer so as to cover continuously thesidewall surface of the contact hole with the gate insulating filminterposed therebetween. An insulating film is provided on the substrateso as to fill the recessed portion of the silicon thin film. The siliconthin film is divided into three portions of a cylindrical channelportion positioned at a portion surrounded by the gate electrode, asource region and a drain region sandwiching the channel portion *fromupper and lower sides. The thickness of the silicon thin film in thechannel portion is equal to or less than the maximum depletion layerwidth.

[0052] According to a third aspect of the present invention, asemiconductor device controls a flow of majority carriers by a voltageapplied to the gate. The semiconductor device includes a substratehaving a main surface. A first conductive layer of a first conductivitytype serving as one source/drain region is provided in the main surfaceof the substrate. A first interlayer insulating film is provided on thesubstrate. A gate electrode having an upper surface and a lower surfaceis provided on the first interlayer insulating film. A second interlayerinsulating film is provided on the first interlayer insulating film soas to cover the gate electrode. A contact hole for exposing a part ofthe surface of the first conductive layer is provided so as to penetratethrough the first interlayer insulating film, the gate electrode, andthe second interlayer insulating film. A sidewall surface of the contacthole is covered with a first gate insulating film. A silicon thin filmis provided in contact with the first conductive layer so as to covercontinuously an inner wall surface of the contact hole with the firstgate insulating film interposed therebetween. The silicon thin film hasa recessed portion having its bottom surface positioned below the lowersurface of the gate electrode in the contact hole. The silicon thin filmis divided into three portions of a cylindrical channel portionpositioned at a portion surrounded by the first gate electrode, a sourceregion and a drain region sandwiching the channel portion from upper andlower sides. The thickness of the silicon thin film in the channelportion is made equal to or less than the maximum depletion layer width.A second gate insulating film is provided on the substrate so as tocover the recessed portion of the silicon thin film. The semiconductordevice further includes a second gate electrode filling the recessedportion of the silicon thin film so as to oppose the channel portionwith the second gate insulting film interposed therebetween.

[0053] According to a fourth aspect of the present invention, asemiconductor device stores information by a gate transistor in acapacitor formed of a storage node, a capacitor insulating film, and acell plate electrode, provided at a crossing point of a bit line and aword line. The semiconductor device includes a substrate having a mainsurface. A first impurity diffusion layer of a first conductivity typeis provided in the main surface of the substrate by implantation ofimpurity of a first conductivity type. The first impurity diffusionlayer serves as one source/drain region and also as the bit line. Afirst interlayer insulating film is provided on the substrate. A gateelectrode having an upper surface and a lower surface is provided on thefirst interlayer insulating film. A second interlayer insulating film isprovided on the first interlayer insulating film so as to cover the gateelectrode. A contact hole for exposing a part of the surface of thefirst impurity diffusion layer is provided so as to penetrate throughthe first interlayer insulating film, the gate electrode, and the secondinterlayer insulating film. A sidewall surface of the contact hole iscovered with a gate insulating film. A first semiconductor layer of afirst conductivity type is formed on the surface of the first impuritydiffusion layer in contact therewith up to the lower surface of the gateelectrode in the contact hole. A channel semiconductor layer is formedon the surface of the first semiconductor layer in contact therewith upto the upper surface of the gate electrode in the contact hole. A secondconductive layer of a first conductivity type is provided on the channelsemiconductor layer in contact with the surface of the channelsemiconductor layer. The second conductive layer serves as the othersource/drain region and also as the storage node. A capacitor insulatingfilm is provided on the second conductive layer. A cell plate electrodeis provided on the storage node with the capacitor insulating filminterposed therebetween.

[0054] According to a fifth aspect of the present invention, asemiconductor device stores information by a gate transistor in acapacitor formed of a storage node, a capacitor insulating film, and acell plate electrode, provided at a crossing point of a bit line and aword line. The semiconductor device includes a substrate having a mainsurface. A first conductive layer of a first conductivity type servingas one source/drain region is provided in the main surface of thesubstrate. A first interlayer insulating film is provided on thesubstrate. A gate electrode having an upper surface and a lower surfaceis provided on the first interlayer insulating film. A second interlayerinsulating film is provided on the first interlayer insulting film so asto cover the gate electrode. A contact hole for exposing a part of thesurface of the first conductive layer is provided so as to penetratethrough the first interlayer insulating film, the gate electrode, andthe second interlayer insulating film. A sidewall surface of the contacthole is covered with a gate insulating film. A silicon thin film isprovided in contact with the first conductive layer, so as to covercontinuously the sidewall surface of the contact hole with the gateinsulating film interposed therebetween The silicon thin film includes arecessed portion having its bottom surface positioned below the lowersurface of the gate electrode in the contact hole. The silicon thin filmis divided into three portions of a cylindrical channel portionpositioned at a portion surrounded by the gate electrode, onesource/drain region positioned on the lower side and the othersource/drain region positioned on the upper side, both sandwiching thechannel portion from the opposite sides. The thickness of the siliconthin film in the channel portion is made equal to or less than themaximum depletion layer width. The other source/drain region is alsoused as a storage node. A capacitor insulating film is provided on thesubstrate so as to cover the recessed portion of the silicon thin film.The semiconductor device includes a cell plate electrode provided on thesubstrate so as to cover the silicon thin film with the capacitorinsulating film interposed therebetween and to fill the recessed portionof the silicon thin film.

[0055] According to a sixth aspect of the present invention, asemiconductor device stores information by a gate transistor in acapacitor formed of a storage node, a capacitor insulating film, and acell plate electrode, provided at a crossing point of a bit line and aword line. The semiconductor device includes a substrate having a mainsurface. A first conductive layer of a first conductivity type servingas one source/drain region is provided in the main surface of thesubstrate. A first interlayer insulating film is provided on thesubstrate. A gate electrode having an upper surface and a lower surfaceis provided on the first interlayer insulating film. A second interlayerinsulating film is provided on the first interlayer insulating film soas to cover the gate electrode. A first contact hole for exposing a partof the surface of the first conductive layer is provided so as topenetrate through the first interlayer insulating film, the gateelectrode, and the second interlayer insulating film. A sidewall surfaceof the first contact hole is covered with a gate insulating film. Asilicon thin film is provided in contact with the first conductive layerso as to cover continuously an inner wall surface of the first contacthole with the gate insulating film interposed therebetween. The siliconthin film includes a recessed portion having its bottom surfacepositioned below the lower surface of the gate electrode in the firstcontact hole. The silicon thin film is divided into three portions of acylindrical channel portion positioned at a portion surrounded by thegate electrode, one source/drain region positioned on the lower side andthe other source/drain region positioned on the upper side, bothsandwiching the channel portion from the opposite sides. The thicknessof the silicon thin film in the channel portion is made equal to or lessthan the maximum depletion layer width. A third interlayer insulatingfilm is provided on the substrate so as to cover the silicon thin film.A second contact hole for exposing a part of the surface of the othersource/drain region is provided in the third interlayer insulating film.A storage node is provided in contact with the other source/drain regionso as to cover an inner wall surface of the second contact hole. Acapacitor insulating film is provided on the substrate so as to coverthe surface of the storage node. A cell plate electrode is provided onthe substrate opposite to the storage node with the capacitor insulatingfilm interposed therebetween so as to fill the second contact hole.

[0056] According to a seventh aspect of the present invention, asemiconductor device inverts logics of an input signal and an outputsignal. The semiconductor device includes a substrate, and a conductivelayer provided on the substrate. A first interlayer insulating film isprovided on the substrate so as to cover the conductive layer. A gateelectrode having an upper surface and a lower surface is provided on thefirst interlayer insulating film. A second interlayer insulating film isprovided on the substrate so as to cover the gate electrode. A firstcontact hole for exposing one part of the surface of the conductivelayer is provided so as to penetrate through the first interlayerinsulating film, the gate electrode, and the second interlayerinsulating film. A second contact hole for exposing another part of thesurface of the conductive layer is provided so as to penetrate throughthe first interlayer insulating film, the gate electrode, and the secondinterlayer insulating film. An inner wall surface of the first contacthole is covered with a gate insulating film. An inner wall surface ofthe second contact hole is covered with a gate insulating film. A firstp⁺ semiconductor layer serving as one source/drain region is formed onthe surface of the conductive layer in contact with the one part thereofup to the lower surface of the gate electrode in the first contact hole.An n⁻ semiconductor layer is formed on the surface of the p⁺semiconductor layer in contact therewith up to the upper surface of thegate electrode in the first contact hole. A second p⁺ semiconductorlayer serving as the other source/drain region is provided on the n⁻semiconductor layer in contact therewith. A first n⁺ semiconductor layerserving as one source/drain region is formed on the surface of theconductive layer in contact with the another part thereof up to thelower surface of the gate electrode in the second contact hole. A p⁻semiconductor layer is formed on the surface of the first n⁺semiconductor layer in contact therewith up to the upper surface of thegate electrode in the second contact hole. A second n⁺ semiconductorlayer serving as the other source/drain region is provided on the p⁻semiconductor layer in contact with the surface of the p⁻ semiconductorlayer.

[0057] According to an eighth aspect of the present invention, asemiconductor device inverts logics of an input signal and an outputsignal. The semiconductor device includes a semiconductor substratehaving a main surface. A field oxide film is formed in the main surfaceof the semiconductor substrate. An n⁺ impurity diffusion layer isprovided in the main surface of the semiconductor substrate directlyunder the field oxide film. A gate electrode having an upper surface anda lower surface is provided on the field oxide film. An interlayerinsulating film is provided on the semiconductor substrate so as tocover the gate electrode. A first contact hole for exposing one part ofthe surface of the n⁺ impurity diffusion layer is provided so as topenetrate through the interlayer insulating film, the gate electrode,and the field oxide film. A second contact hole for exposing anotherpart of the surface of the n⁺ impurity diffusion layer is provided so asto penetrate through the interlayer insulating film, the gate electrode,and the field oxide film. An inner wall surface of the first contacthole is covered with the gate insulating film. An inner wall surface ofthe second contact hole is covered with a gate insulating film. Aconductor film is provided in contact with the one part of the n⁺impurity diffusion layer in the first contact hole. A first p⁺semiconductor layer serving as one source/drain region is formed on thesurface of the conductor film in contact therewith up to the lowersurface of the gate electrode in the first contact hole. An n⁻semiconductor layer is formed on the surface of the first p⁺semiconductor layer in contact therewith up to the upper surface of thegate electrode in the first contact hole. A second p⁺ semiconductorlayer serving as the other source/drain region is provided on the n⁻semiconductor layer in contact therewith. A first n⁺ semiconductor layerserving as one source/drain region is formed on the surface of the n⁺impurity diffusion layer in contact with the another part thereof up tothe lower surface of the gate electrode in the second contact hole. A p⁻semiconductor layer is formed on the surface of the first n⁺semiconductor layer in contact therewith up to the upper surface of thegate electrode in the second contact hole. A second n⁺ semiconductorlayer serving as the other source/drain region is provided on the p⁻semiconductor layer in contact therewith.

[0058] According to a ninth aspect of the present invention, asemiconductor device inverts logics of an input signal and an outputsignal. The semiconductor device includes a semiconductor substratehaving a main surface. A field oxide film is formed in the main surfaceof the semiconductor substrate. A p⁺ impurity diffusion layer and an n⁺impurity diffusion layer are formed in the main surface of thesemiconductor substrate with being separated from each other by thefield oxide film. A first interlayer insulating film is provided on thesemiconductor substrate. A gate electrode is provided on the firstinterlayer insulating film so as to cover the p⁺ impurity diffusionlayer and the n⁺ impurity diffusion layer. A second interlayerinsulating film is provided on the semiconductor substrate so as tocover the gate electrode. A first contact hole for exposing one part ofthe surface of the p⁺ impurity diffusion layer is provided so as topenetrate through the first interlayer insulating film, the gateelectrode, and the second interlayer insulating film. A second contacthole for exposing one part of the surface of the n⁺ impurity diffusionlayer is provided so as to penetrate through the first interlayerinsulating film, the gate electrode, and the second interlayerinsulating film. An inner wall surface of the first contact hole iscovered with a gate insulating film. An inner wall surface of the secondcontact hole is covered with a gate insulating film. A first p⁺semiconductor layer serving as one source/drain region is provided onthe surface of the p⁺ impurity diffusion layer in contact therewith upto the lower surface of the gate electrode in the first contact hole. Ann⁻ semiconductor layer is formed on the surface of the first p⁺semiconductor layer in contact therewith up to the upper surface of thegate electrode in the first contact hole. A second p⁺ semiconductorlayer serving as the other source/drain region is provided on the n⁻semiconductor layer. A first n⁺ semiconductor layer serving as onesource/drain region is formed on the surface of the n⁺ impuritydiffusion layer in contact therewith up to the lower surface of the gateelectrode in the second contact hole. A p⁻ semiconductor layer is formedon the surface of the first n⁺ semiconductor layer in contact therewithup to the upper surface of the gate electrode in the second contacthole. A second n⁺ semiconductor layer serving as the other source/drainregion is provided on the p⁻ semiconductor layer in contact therewith.An end portion of the second p⁺ semiconductor layer and an end portionof the second n⁺ semiconductor layer are contact with each other at anupper portion of the field oxide film. The semiconductor device furtherincludes a connection member electrically connecting the surface of thesecond p⁺ semiconductor layer and the surface of the second n⁺semiconductor layer.

[0059] According to a tenth aspect of the present invention, asemiconductor device serves as a logic circuit in a cooperativeoperation of a first transistor and a second transistor. Thesemiconductor device includes a substrate, and an SiO₂ layer provided onthe substrate. A semiconductor layer having an upper surface and a lowersurface is provided on the SiO₂ layer. A gate electrode of the firsttransistor is provided on the semiconductor layer with an insulatingfilm interposed therebetween. The semiconductor device includes a pairof source/drain regions of the first transistor provided in thesemiconductor layer and spaced from each other on the opposite sides ofthe gate electrode. A contact hole for exposing one part of the surfaceof the substrate is provided at a position distant from the gateelectrode of the first transistor so as to penetrate through one of thesource/drain regions and the SiO₂ layer. An inner wall surface of thecontact hole is covered with a gate insulating film of the secondtransistor. One source/drain layer of the second transistor is formed onthe surface of the substrate in contact therewith up to the lowersurface of the semiconductor layer in the contact hole. A channel layerof the second transistor is formed on the surface of the onesource/drain layer of the second transistor in contact therewith up tothe upper surface of the semiconductor layer in the contact hole. Theother source/drain layer of the second transistor is provided on thechannel layer of the second transistor in contact therewith.

[0060] According to an eleventh aspect of the present invention, asemiconductor device inverts logics of an input signal and an outputsignal in a cooperative operation of a first transistor and a secondtransistor. The semiconductor device includes a substrate and a firstinsulating film provided on the substrate. A gate electrode of the firsttransistor having an upper surface and a lower surface is provided onthe first insulating film. A second insulating film is provided on thesubstrate so as to cover the gate electrode of the first transistor. Acontact hole for exposing one part of the surface of the substrate isprovided so as to penetrate through the gate electrode of the firsttransistor and the second insulating film. One source/drain layer of thesecond transistor is provided in the main surface of the substratedirectly under the contact hole. An inner wall surface of the contacthole is covered with a gate insulating film of the second transistor. Achannel layer of the second transistor is formed on the surface of theone source/drain layer of the second transistor in contact therewith upto the upper surface of the gate electrode in the contact hole. Theother source/drain layer of the second transistor is provided on thechannel layer of the second transistor in contact therewith.

[0061] According to a twelfth aspect of the present invention, asemiconductor device stores information in a cooperative operation offour transistors. The semiconductor device includes a flip-flop formedusing two inverter circuits according to the ninth aspect, and twotransistors.

[0062] According to a thirteenth aspect of the present invention, asemiconductor device stores information in a cooperative operation offour transistors. The semiconductor device is characterized in that atransistor according to the first aspect of the present invention isused as an access transistor.

[0063] According to a fourteenth aspect of the present invention, asemiconductor device stores information in a cooperative operation offour transistors. The semiconductor device is characterized in thattransistors according to the first aspect of the present invention areused as an access transistor and a load transistor.

[0064] In a method of manufacturing a semiconductor device according toa fifteenth aspect of the present invention, a first conductive layer isformed including impurity of a first conductivity type and serving asone source/drain region in the main surface of a substrate. A firstinterlayer insulating film is formed on the substrate. A gate electrodehaving an upper surface and a lower surface is formed on the firstinterlayer insulating film. A second interlayer insulating film isformed on the substrate so as to cover the gate electrode. A contacthole is formed penetrating through the first interlayer insulating film,the gate electrode, and the second interlayer insulating film into thesurface of the first conductive layer. A sidewall surface of the contacthole is covered with a gate insulating film. A semiconductor layer isformed on the substrate in contact with the surface of the firstconductive layer so as to fill the contact hole. Impurity of a firstconductivity type is implanted into the surface of the semiconductorlayer. The impurity implanted into the surface of the semiconductorlayer is diffused in the semiconductor layer, and the impurity includedin the first conductive layer is diffused from the first conductivelayer to the semiconductor layer, whereby the other source/drain regionand a channel region sandwiched by the other source/drain region and theone source/drain region are formed in the semiconductor layer.

[0065] According to a method of manufacturing a semiconductor device inaccordance with a sixteenth aspect of the present invention, asemiconductor device controlling a flow of majority carriers by avoltage applied to the gate is manufactured. A silicon nitride film isformed on the surface of a substrate. A first conductive layer includingimpurity of a first conductivity type and serving as one source/drainregion is formed in the main surface of the substrate by implantingimpurity into the surface of the substrate through the silicon nitridefilm. A first interlayer insulating film is formed on the substrate soas to cover the silicon nitride film. A gate electrode having an uppersurface and a lower surface is formed on the first interlayer insulatingfilm. A second interlayer insulating film is formed on the substrate soas to cover the gate electrode. A contact hole is formed penetratingthrough the first interlayer insulating film, the gate electrode, andthe second interlayer insulating film into the surface of the siliconnitride film. A sidewall surface of the contact hole is oxidized to forma gate insulating film. An exposed surface of the silicon nitride filmis etched for exposure of the surface of the first conductive layer. Asemiconductor layer is formed on the substrate in contact with thesurface of the exposed first conductive layer so as to fill the contacthole. Impurity of a first conductivity type is implanted into thesurface of the semiconductor layer. The impurity implanted into thesurface of the semiconductor layer is diffused in the semiconductorlayer, and the impurity included in the first conductive layer isdiffused from the first conductive layer to the semiconductor layer,whereby the other source/drain region and a channel region sandwiched bythe other source/drain region and the one source/drain region are formedin the semiconductor layer.

[0066] A method of manufacturing a semiconductor device according to aseventeenth aspect of the present invention relates to a method ofmanufacturing a semiconductor device controlling a flow of majoritycarriers by a voltage applied to the gate. A first source/draindrawing-out electrode is formed in the main surface of the substrate fordrawing out a source/drain electrode to an external terminal. A firstinterlayer insulating film, a gate electrode and a second interlayerinsulating film are sequentially deposited on the substrate. A contacthole is formed penetrating through the first interlayer insulating film,the gate electrode and the second interlayer insulating film forexposing one part of the surface of the first source/drain drawing-outelectrode. An inner wall surface of the contact hole is covered with agate insulating film. A first epitaxial silicon layer including impurityof a first conductivity type, a second epitaxial silicon layer includingimpurity of a second conductivity type, and a third epitaxial siliconlayer including impurity of a first conductivity type are sequentiallyformed in the contact hole. A second source/drain drawing-out electrodeis formed on the third epitaxial silicon layer.

[0067] A method of manufacturing a semiconductor device according to aneighteenth aspect of the present invention relates to a method ofmanufacturing a semiconductor device controlling a flow of majoritycarriers by a voltage applied to the gate. Formed in the main surface ofa substrate is a first conductive layer including impurity of a firstconductivity type and serving as one source/drain region. A firstinterlayer insulating film is formed on the substrate. A gate electrodehaving an upper surface and a lower surface is formed on the firstinterlayer insulating film. A second interlayer insulating film isformed on the substrate so as to cover the gate electrode. A contacthole is formed penetrating through the first interlayer insulating film,the gate electrode, and the second interlayer insulating film into thesurface of the first conductive layer. A sidewall surface of the contactwall is covered with a gate insulating film. A semiconductor film isformed on the substrate so as to cover the surface of the firstconductive layer and an inner wall surface of the contact wall. Impurityof a first conductivity type is implanted into the surface of thesemiconductor film by a rotational ion implantation method. The impurityimplanted into the surface of the semiconductor film is diffused in thesemiconductor film, and the impurity included in the first conductivelayer is diffused from the first conductive layer to the semiconductorfilm, whereby the other source/drain region and a channel regionsandwiched by the other source/drain region and the one source/drainregion are formed in the semiconductor film. An insulating film fillsthe contact hole in contact with the semiconductor film.

[0068] A method of manufacturing a semiconductor device according to anineteenth aspect of the present invention relates to a method ofmanufacturing a semiconductor device controlling a flow of majoritycarriers by a voltage applied to the gate. Formed in the main surface ofthe substrate is a first conductive layer including impurity of a firstconductivity type and serving on one source/drain region. A firstinterlayer insulating film is formed on the substrate. A gate electrodehaving an upper surface and a lower surface is formed on the firstinterlayer insulating film. A second interlayer insulating film isformed on the substrate so as to cover the gate electrode. A contacthole is formed penetrating through the first interlayer insulating film,the gate electrode, and the second interlayer insulating film into thesurface of the first conductive layer. A sidewall surface of the contacthole is covered with a gate insulating film. A semiconductor film isformed on the substrate so as to cover the surface of the firstconductive layer and an inner wall surface of the contact hole. A firstinsulating film is formed on the sidewall surface of the contact holewith the semiconductor film interposed therebetween. Impurity of a firstconductivity type is implanted into the surface of the semiconductorfilm in a direction perpendicular to the substrate with the firstinsulating film used as a mask. The impurity implanted into the surfaceof the semiconductor film is diffused in the semiconductor film, and theimpurity included in the first conductive layer is diffused from thefirst conductive layer to the semiconductor film, whereby the othersource/drain region and a channel region sandwiched by the othersource/drain region and the one source/drain region are formed in thesemiconductor film. A second insulating film fills the contact hole withthe first insulating film and the semiconductor film interposedtherebetween.

[0069] A method of manufacturing a semiconductor device according to atwentieth aspect of the present invention relates to a method ofmanufacturing a semiconductor device controlling a flow of majoritycarriers by a voltage applied to the gate. Formed in the main surface ofthe substrate is a first conductive layer including impurity of a firstconductivity type and serving as one source/drain region. A firstinterlayer insulating film is formed on the substrate. A gate electrodehaving an upper surface and a lower surface is formed on the firstinterlayer insulating film. A second interlayer insulating film isformed on the substrate so as to cover the gate electrode. A contacthole is formed penetrating through the first interlayer insulating film,the gate electrode and the second interlayer insulating film into thesurface of the first conductive layer. A sidewall surface of the contactwall is covered with a gate insulating film. A semiconductor film isformed on the substrate so as to cover the surface of the firstconductive layer and an inner wall surface of the contact hole. Aninsulating film fills the contact hole in contact with the semiconductorfilm. Impurity of a first conductivity type is implanted into thesurface of the semiconductor film. The impurity implanted into thesurface of the semiconductor film is diffused in the semiconductor film,and the impurity included in the first conductive layer is diffused fromthe first conductive layer to the semiconductor film, whereby the othersource/drain region and a channel region sandwiched by the othersource/drain region and the one source/drain are formed in thesemiconductor film.

[0070] A method of manufacturing a semiconductor device according to atwenty-first aspect of the present invention relates to a method ofmanufacturing a semiconductor device controlling a flow of majoritycarriers by a voltage applied to the gate. Formed in the main surface ofa substrate is a first conductive layer including impurity of a firstconductivity type and serving as one source/drain region. A firstinterlayer insulating film is formed on the substrate. A first gateelectrode having an upper surface and a lower surface is formed on thefirst interlayer insulating film. A second interlayer insulating film isformed on the substrate so as to cover the first gate electrode. Acontact hole is formed penetrating through the first interlayerinsulating film, the first gate electrode, and the second interlayerinsulating film into the surface of the first conductive layer. Asidewall surface of the contact hole is covered with a first gateinsulating film. A semiconductor film is formed in contact with thesurface of the first conductive layer so as to cover an inner wallsurface of the contact hole with the first gate insulating filminterposed therebetween. Formed in the semiconductor film are onesource/drain region in contact with the first conductive layer, achannel region connected to the one source/drain region, and the othersource/drain region connected to the channel region. A second gateinsulating film covering an inner wall surface of the contact hole isformed on the substrate with the semiconductor film interposedtherebetween. A second gate electrode fills the contact hole so as tooppose the semiconductor film with the second gate insulating filminterposed therebetween.

[0071] A method of manufacturing a semiconductor device according to atwenty-second aspect of the present invention relates to a method ofmanufacturing a semiconductor device controlling a flow of majoritycarriers by a voltage applied to the gate. Formed in the main surface ofa substrate is a first conductive layer including impurity of a firstconductivity type and serving as one source/drain region. A firstinterlayer insulating film is formed on the substrate. A gate electrodehaving an upper surface and a lower surface is formed on the firstinterlayer insulating film. A second interlayer insulating film isformed on the substrate so as to cover the gate electrode. A contacthole is formed penetrating through the first interlayer insulating film,the gate electrode and the second interlayer insulating film into thesurface of the first conductive layer. A sidewall surface of the contacthole is covered with a gate insulating film. A semiconductor layer isformed on the substrate so as to fill the contact hole. One source/drainregion of a first conductivity type connected to the first conductivelayer is formed in the semiconductor layer. A channel region of a secondconductivity type connected to the one source/drain region is formed inthe semiconductor layer. A region of a low concentration of the othersource/drain region of a first conductivity type connected to thechannel region is formed in the semiconductor layer. A region of a highconcentration of the other source/drain region of a first conductivitytype is formed in the semiconductor layer so as to be connected to theregion of a low concentration.

[0072] The semiconductor device according to the first aspect of thepresent invention occupies a small area since a vertical type surroundgate is employed.

[0073] In the semiconductor device according to the second aspect of thepresent invention, it is possible to completely deplete the entirechannel since the thickness of the silicon thin film in the channel isequal to or less than the maximum depletion layer width or less.

[0074] In the semiconductor device according to the third aspect of thepresent invention, it is possible to reduce an off current of atransistor and to improve an on current of the transistor since thedevice includes two gate electrodes.

[0075] In the semiconductor device according to the fourth aspect of thepresent invention, that is, in a dynamic random access memory, an areaoccupied by the DRAM is small since a contact hole transistor is used.

[0076] In the semiconductor device according to the fifth and sixthaspects of the present invention, that is, in a DRAM, an area occupiedby the DRAM is small since a contact hole transistor is used.

[0077] In the inverter circuit according to the seventh aspect of thepresent invention, an area occupied by the inverter circuit is smallsince a contact hole transistor is used.

[0078] In the inverter circuit according to the eighth aspect of thepresent invention, the surface of the semiconductor substrate can beeffectively used since the inverter circuit is formed on the field oxidefilm.

[0079] In the inverter circuit according to the ninth aspect of thepresent invention, contact is easily made and an area occupied by theinverter circuit is small since Vout is provided at the upper portion ofthe substrate.

[0080] In the logic circuit according to the tenth aspect of the presentinvention, an area occupied by the logic circuit is small since an SOItransistor and a contact hole transistor are used to form the invertercircuit.

[0081] In the inverter circuit according to the eleventh aspect of thepresent invention, an area occupied by the inverter circuit can be madesmall since an MOS transistor and a contact hole transistor are combinedto form the inverter circuit.

[0082] In the semiconductor device according to the twelfth, thirteenth,and fourteenth aspects of the present invention, a static random accessmemory occupying a small area can be obtained.

[0083] According to the method of manufacturing a semiconductor deviceof the fifteenth aspect of the present invention, the impurity implantedinto the surface of the semiconductor layer is diffused in thesemiconductor layer and the impurity included in the first conductivelayer is diffused from the first conductive layer to the semiconductorlayer, whereby the other source/drain region and a channel regionsandwiched by the other source/drain region and the one source/drainregion are formed in the semiconductor layer. Therefore, thesource/drain region and the channel region can be formed simultaneouslyby one time thermal diffusion.

[0084] According to the method of manufacturing a semiconductor deviceof the sixteenth aspect of the present invention, since the gateinsulating film is formed by oxidation of the sidewall surface of thecontact hole, the method of forming the gate insulating film can befacilitated.

[0085] According to the method of manufacturing a semiconductor deviceof the seventeenth aspect of the present invention, since the channelregion is formed by epitaxial growth, crystallization of the channelregion is enhanced, which in turn improves the transistorcharacteristics. Since the conductivity type of the semiconductor can bechanged by only changing gas at the time of growth of an epitaxiallayer, the process can be simplified.

[0086] According to the method of manufacturing a semiconductor deviceof the eighteenth aspect of the present invention, since impurity of afirst conductivity type is implanted into the surface of thesemiconductor film by a rotational ion implantation method, the impuritycan be implanted into the inner wall surface of the contact hole.

[0087] According to the method of manufacturing a semiconductor of thenineteenth aspect of the present invention, since impurity of a firstconductivity type is implanted into the surface of the semiconductorfilm with the first insulating film used as a mask in a directionperpendicular to the substrate, the impurity is not implanted into thechannel portion even if the implantation angle is slightly offset. As aresult, a leakage current between source and drain is not generated.

[0088] According to the method of manufacturing a semiconductor deviceof the twentieth aspect of the present invention, impurity of a firstconductivity type is implanted into the surface of the semiconductorfilm after filling the contact hole with the insulating film in contactwith the semiconductor film. Then, the impurity implanted into thesurface of the semiconductor film is diffused in the semiconductor filmto form the other source/drain region. Therefore, the impurity is notimplanted into the bottom portion of the semiconductor film. As aresult, the impurity is not diffused into the channel region by heattreatment to be applied later, not causing the short channel effect.Leakage current between source and drain is not generated.

[0089] According to the method of manufacturing a semiconductor deviceof the twenty-first aspect of the present invention, since a transistorhaving two gate electrodes can be formed, it is possible to reduce theoff current of the transistor and to improve the on current of thetransistor.

[0090] According to the method of manufacturing a semiconductor deviceof the twenty-second aspect of the present invention, since thesource/drain, the channel, the LDD portion are formed by high energy ionimplantation, the formation can be facilitated.

[0091] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0092]FIG. 1 is a perspective view of a vertical type surround gatefield effect transistor (contact hole transistor) according to oneembodiment of the present invention.

[0093]FIG. 2 is a cross sectional view showing the contact holetransistor shown in FIG. 1.

[0094]FIG. 3 is a diagram for explaining operation of the contact holetransistor according to the present invention.

[0095] FIGS. 4 to 12 are partial cross sectional views of asemiconductor device in the first to the ninth steps of a method ofmanufacturing the contact hole transistor according to Embodiment 1A ofthe present invention.

[0096]FIG. 13 is a diagram showing various manners of a shape of acontact hole used in the contact hole transistor of the presentinvention.

[0097] FIGS. 14 to 21 are partial cross sectional views of asemiconductor device in the first to the eighth steps of a method ofmanufacturing the contact hole transistor according to Embodiment 2A ofthe present invention.

[0098] FIGS. 22 to 27 are partial cross sectional views of asemiconductor device in the first to the sixth steps of a further methodof manufacturing the contact hole transistor of the present invention.

[0099]FIG. 28 is a cross sectional view of a contact hole transistoraccording to a further embodiment of the contact hole transistor of thepresent invention.

[0100] FIGS. 29 to 32 are partial cross sectional views of asemiconductor device in the first to the fourth steps of a furthermethod of manufacturing the contact hole transistor shown in FIG. 28.

[0101] FIGS. 33 to 35 are partial cross sectional views of asemiconductor device in the first to the third steps of a further methodof manufacturing the contact hole transistor shown in FIG. 28.

[0102]FIG. 36 is a diagram showing problems of a manufacturing methodaccording to Embodiment 6.

[0103]FIG. 37 is a cross sectional view of a contact hole transistoraccording to a further embodiment of the present invention.

[0104]FIG. 38 is a cross sectional view of a contact hole transistoraccording to a further embodiment of the present invention.

[0105]FIG. 39 is a pattern layout diagram of a DRAM cell according toEmbodiment 10.

[0106]FIG. 40 is a perspective view showing in three dimensions one cellof the DRAM shown in FIG. 39.

[0107]FIG. 41 is a cross sectional view of the DRAM cell shown in FIG.39.

[0108]FIG. 42 is an equivalent circuit diagram of the DRAM cell shown inFIG. 39.

[0109]FIG. 43 is a perspective view of a DRAM cell according toEmbodiment 11.

[0110]FIG. 44 is a cross sectional view of a DRAM cell according toEmbodiment 12.

[0111]FIG. 45 is a cross sectional view of a DRAM cell according toEmbodiment 13.

[0112] FIGS. 46 to 49 are partial cross sectional views of asemiconductor device in the first to the fourth steps of a method ofmanufacturing a semiconductor memory device shown in FIG. 45.

[0113]FIG. 50 is a cross sectional view of a DRAM cell according toEmbodiment 14.

[0114]FIGS. 51 and 52 are partial cross sectional views of asemiconductor device in the first and the second steps of a main partsof a method of manufacturing the DRAM cell shown in FIG. 50.

[0115]FIG. 53 is a cross sectional view of a DRAM cell according toEmbodiment 15.

[0116] FIGS. 54 is a cross sectional view of an inverter circuitaccording to Embodiment 16.

[0117]FIG. 55 is a plan view of the inverter circuit according toEmbodiment 16.

[0118]FIG. 56 is an equivalent circuit diagram of the inverter circuitaccording to Embodiment 16.

[0119]FIGS. 57 and 58 are partial cross sectional views of asemiconductor device in the first and the second steps of a method ofmanufacturing the inverter circuit shown in FIG. 54.

[0120]FIG. 59 is a cross sectional view of a semiconductor deviceaccording to a modification of Embodiment 16.

[0121]FIG. 60 is a diagram showing another modification of the invertercircuit according to Embodiment 16.

[0122]FIG. 61 is a cross sectional view of a still another modificationof the inverter circuit according to Embodiment 16.

[0123]FIG. 62 is a cross sectional view of a device of a furthermodification of the inverter circuit according to Embodiment 16.

[0124]FIG. 63 is a cross sectional view of an inverter circuit accordingto Embodiment 17.

[0125] FIGS. 64 to 67 are cross sectional views of a semiconductordevice in the first to the fourth steps of a method of manufacturing theinverter circuit shown in FIG. 63.

[0126]FIG. 68 is a cross sectional view of an inverter circuit accordingto Embodiment 18.

[0127]FIG. 69 is a cross sectional view of an inverter circuit accordingto Embodiment 19.

[0128]FIG. 70 is a cross sectional view of an inverter circuit accordingto Embodiment 20.

[0129]FIG. 71 is a cross sectional view of an inverter circuit accordingto a modification of Embodiment 20.

[0130]FIG. 72 is a cross sectional view of an inverter circuit accordingto Embodiment 21.

[0131]FIG. 73 is a plan view of the inverter circuit according toEmbodiment 21.

[0132]FIG. 74 is a layout diagram of the first layer of an SRAM cellaccording to Embodiment 22.

[0133]FIG. 75 is a layout diagram of the second layer of the SRAM cellaccording to Embodiment 22.

[0134]FIG. 76 is a layout diagram of the third layer of the SRAM cellaccording to Embodiment 22.

[0135]FIG. 77 is an equivalent circuit diagram of the SRAM cellaccording to Embodiment 22.

[0136]FIG. 78 is a cross sectional view taken along the line C-C in FIG.75.

[0137]FIG. 79 is a cross sectional view taken along the line D-D in FIG.75.

[0138]FIG. 80 is a cross sectional view showing a method of forming agate insulating film of an access transistor large in thickness.

[0139]FIG. 81 is a cross sectional view of a logic circuit according toEmbodiment 23.

[0140]FIG. 82 is a perspective view of a portion of an SOI transistor ofthe logic circuit shown in FIG. 81.

[0141]FIG. 83 is an equivalent circuit diagram of the logic circuitaccording to Embodiment 23.

[0142]FIG. 84 is a pattern layout diagram of an inverter circuitaccording to Embodiment 24.

[0143]FIG. 85 is a cross sectional view taken along the line A-A in FIG.84.

[0144]FIG. 86 an equivalent circuit diagram of the inverter circuitaccording to Embodiment 24.

[0145]FIG. 87 is a cross sectional view of a device of a modification ofthe inverter circuit according to Embodiment 24.

[0146]FIG. 88 is a cross sectional view of a further modification of theinverter circuit according to Embodiment 24.

[0147]FIG. 89 is an equivalent circuit diagram of an SRAM memory cellaccording to Embodiment 25.

[0148]FIG. 90 is a layout diagram of the lower layer of the SRAM memorycell according to Embodiment 25.

[0149]FIG. 91 is a layout diagram of the intermediate layer of the SRAMmemory cell according to Embodiment 25.

[0150]FIG. 92 is a layout diagram of the upper layer of the SRAM memorycell according to Embodiment 25.

[0151]FIG. 93 is a cross sectional view taken along the lines A-A ofFIGS. 90 to 92.

[0152]FIG. 94 is a cross sectional view taken along the lines B-B inFIGS. 90 to 92.

[0153]FIG. 95 is a perspective view of a field effect transistor used inEmbodiment 25.

[0154]FIG. 96 is a layout diagram of the lower layer of an SRAM memorycell according to Embodiment 26.

[0155]FIG. 97 is a layout diagram of the intermediate layer of the SRAMmemory cell according to Embodiment 26.

[0156]FIG. 98 is a layout diagram of the upper layer of the SRAM memorycell according to Embodiment 26.

[0157]FIG. 99 is a cross sectional view taken along the lines C-C inFIGS. 96 to 98.

[0158]FIG. 100 is a cross sectional view taken along the lines D-D inFIGS. 96 to 98.

[0159]FIG. 101 is a schematic diagram of a conventional planar typeMOSFET.

[0160]FIG. 102 is a perspective view extracting and illustrating mainportions of a conventional vertical type surround gate MOSFET.

[0161]FIG. 103 is a simplified diagram of a transistor shown in FIG.102.

[0162]FIG. 104 is a cross sectional view of a conventional SOIMOSFET.

[0163]FIG. 105 is a graph showing the relationship between a radius Rand a depletion layer capacitance Cd of the conventional vertical typesurround gate MOSFET.

[0164] FIGS. 106 to 110 are partial cross sectional views of asemiconductor device in the first to the fifth steps of a method ofmanufacturing the conventional vertical type surround gate MOSFET.

[0165]FIG. 111 is a perspective view of a plug-shaped silicon of theconventional vertical type surround gate MOSFET.

[0166] FIGS. 112 to 115 are partial cross sectional views of asemiconductor device in the first to the fourth steps of the mainportion of a method of manufacturing a contact hole transistor accordingto Embodiment 1B of the present invention.

[0167]FIG. 116 is a diagram showing a portion which requires improvementof Embodiment 2A.

[0168] FIGS. 117 to 122 are partial cross sectional views of asemiconductor device in the first to the sixth steps of the main portionof a method of manufacturing a contact hole transistor according toEmbodiment 2B of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0169] Description of embodiments of the present invention will be givenhereinafter with reference to the drawings.

[0170] Embodiment 1

[0171] (Embodiment 1A)

[0172]FIG. 1 is a perspective view extracting and illustrating mainportions of a vertical type surround gate MOSFET according to oneembodiment of the present invention. FIG. 2 is a cross sectional view ofthe vertical type surround gate MOSFET according to this embodiment.

[0173] Referring to these figures, the MOSFET includes a substrate 1.Although the case is shown here where an ordinary silicon substrate isused as substrate 1, an SOI substrate may be used. A source region 6 ais provided in the main surface of substrate 1. In the case of aP-channel transistor, P-type impurities are implanted in source region 6a. A first interlayer insulating film 2 a is provided on substrate 1. Agate electrode 3 having an upper end surface substantially parallel tothe surface of the substrate is provided on first interlayer insulatingfilm 2 a. A second interlayer insulating film 2 b is provided on firstinterlayer insulating film 2 a so as to cover gate electrode 3. Acontact hole 19 for exposing a part of the surface of source region 6 ais provided so as to penetrate through first interlayer insulating film2 a, gate electrode 3, and second interlayer insulating film 2 b. Asidewall surface of contact hole 19 is covered with a gate insulatingfilm 4. A first P-type semiconductor layer 20 is provided in contacthole 19 on the surface of source region 6 a in contact therewith up tothe lower surface of gate electrode 3. A channel semiconductor layer 7is provided in contact hole 19 on the surface of first semiconductorlayer 20 in contact therewith up to the upper surface of gate electrode3. A second P-type semiconductor layer 5 serving as a drain region 6 bis provided on the surface of channel semiconductor layer 7 in contacttherewith

[0174] A third interlayer insulating film 2 c is provided on thesubstrate so as to cover drain region 6 b. A connection hole 11 a forexposing a part of the surface of drain region 6 b is provided in thirdinterlayer insulating film 2 c. An aluminum electrode 10 a is connectedto drain region 6 b through connection hole 11 a. The diameter ofchannel semiconductor layer 7 (hereinafter referred to as a “channelportion 7”) is made smaller than the hole diameter of connection hole 11a. Channel portion 7 is cylindrical, with the radius equal to or lessthan the maximum depletion layer width.

[0175]FIG. 3 is a cross sectional view of channel portion 7. FIG. 3(a)schematically shows the case where the radius of channel portion 7 islarger than the maximum depletion layer width, and FIG. 3(b)schematically shows the case where the radius of channel portion 7 issmaller than the maximum depletion layer width.

[0176] Referring to FIG. 3(b), when a voltage is applied to gateelectrode 3, a depletion layer 17 extends inwardly from a sidewallsurface of channel portion 7. The radius of channel portion 7 is smallerthan the maximum depletion layer width. When a depletion layer width Wdreaches a value of the radius of channel portion 7, depletion layer 17can no longer extend. As a result, an inversion layer 18 is immediatelyformed on the sidewall surface of channel portion 7. More specifically,when the radius of channel portion 7 is smaller than the maximumdepletion layer width, a speed increases at which inversion layer 18 isformed. Conversely, as shown in FIG. 3(a), when the radius of channelportion 7 is larger than the maximum depletion layer width, it takestime for the width Wd of depletion layer 17 to reach the maximumdepletion layer width, resulting in decrease of a speed at whichinversion layer 18 is formed.

[0177] FIGS. 4 to 12 are partial cross sectional views of asemiconductor device in respective steps in order of a method ofmanufacturing the MOSFET (hereinafter referred to as a “contact holetransistor”) shown in FIG. 2.

[0178] Referring to FIG. 4, source region 6 a is formed by implantingimpurities into the main surface of substrate 1. In the case of theP-channel transistor, P-type impurities such as boron, are implantedunder the condition of implantation energy of 10 keV and a concentrationof 5×10¹⁵/cm². Interlayer insulating film 2 a of a thickness of 2000 Åis formed on substrate 1. Polysilicon of the film thickness of 1000 Å isdeposited on interlayer insulating film 2 a to form gate electrode 3.

[0179] Referring to FIG. 5, gate electrode 3 is patterned into apredetermined shape. Referring to FIG. 6, interlayer insulating film 2 bof a thickness of 2000 Å is deposited so as to cover gate electrode 3. Aresist pattern 120 having an opening 120 a at a predetermined positionis formed on interlayer insulating film 2 b.

[0180] Referring to FIG. 7, a contact hole 5 a penetrating through firstinterlayer insulating film 2 a, gate electrode 3, and second interlayerinsulating film 2 b to reach the surface of source region 6 a is formedby photolithography and anisotropic etching with resist pattern 120 usedas a mask. The radius of contact hole 5 a is, for example, 0.25 μm.

[0181] Referring to FIG. 8, gate insulating film 4 of a thickness of 200Å is deposited so as to cover a bottom portion 9 and the sidewallsurface of contact hole 5 a. Gate insulating film 4 may be formed byoxidizing the sidewall surface of contact hole 5 a.

[0182] Referring to FIGS. 8 and 9, gate insulating film 4 on bottomportion 9 of the contact hole is removed by anisotropic dry etching.

[0183] Referring to FIGS. 9 and 10, amorphous silicon 5 of a thicknessof 3000 Å is deposited on substrate 1 so as to fill contact hole 5 a. Ifthe film thickness of amorphous silicon 5 is made larger than the radius(R=0.25 μm=2500 Å) of contact hole 5 a, amorphous silicon can completelyfill contact hole 5 a.

[0184] An LPCVD method using SiH₄ gas or Si₂H₆ gas is employed as amethod of forming amorphous silicon 5. When amorphous silicon isdeposited at a temperature of approximately 400° C. to 600° C. andannealed at a temperature of approximately 600° C., a crystal in thesame orientation as that of substrate 1 grows in the surface of bottomportion 9 of the contact hole. As will be described later, the channelportion is mono-crystallized. When impurities are introduced in thechannel portion, doping gas (for example, PH₃, AsH₃ when the channel isintended to be of N⁻ type, and B₂H₆ when the channel is intended to beof P⁻ type) is mixed in the above-described gas to deposit theabove-described amorphous silicon.

[0185] Referring to FIGS. 10 and 11, impurities are implanted into thesurface of amorphous silicon 5 to form drain region 6 b. In the case ofP-channel, P-type impurities such as boron, are implanted under thecondition of implantation energy of 80 keV and a concentration of5×10¹⁵/cm². After heat treatment at 850° C. for approximately 30minutes, impurities are diffused from source region 6 a into amorphoussilicon 5, and from drain region 6 b into amorphus silicon 5, as shownby arrows. By changing the temperature and the time of heat treatment orthe thickness of interlayer insulating films 2 a, 2 b, distribution ofimpurities between channel and source, and between channel and drain canbe changed.

[0186] Referring to FIGS. 11 and 12, third interlayer insulating film 2c is formed on substrate 1. Contact holes connecting to gate electrode3, source region 6 a, and drain region 6 b, respectively, are formed ininterlayer insulating film 3. Formation of aluminum interconnections 10a, 10 b, 10 c in respective contact holes completes a contact holetransistor.

[0187] In the above-described embodiment, the case where the shape ofthe contact hole is circle was taken as an example with reference toFIG. 1. However, the present invention is not limited thereto. Morespecifically, the shape of the contact hole may be rectangular as shownin FIG. 13(b), or L-shaped as shown in FIG. 13(c). When the radius (R)of the biggest inscribed circle inscribed to these polygons is equal toor less than the maximum depletion layer width, it is possible todeplete the entire channel.

[0188]FIG. 13(a) shows a shape of the contact hole shown in FIG. 1. Ifthe radius (R) of the contact hole is made equal to or less than themaximum depletion layer width, the entire channel can be depleted.

[0189] (Embodiment 1B)

[0190] This embodiment shows a more preferred manner of Embodiment 1A.The same process as shown in FIGS. 4 and 5 is first carried out.

[0191] Referring to FIG. 112, second interlayer insulating film 2 b isformed so as to cover gate electrode 3. Second interlayer insulatingfilm 2 b is deposited a little thicker than the case of Embodiment 1A.Resist pattern 120 having opening portion 120 a is formed on secondinterlayer insulating film 2 b at a predetermined portion.

[0192] Referring to FIGS. 112 and 113, with resist pattern 120 used as amask, second interlayer insulating film 2 b is etched. Then, resistpattern 120 is removed.

[0193] Referring to FIG. 114, gate electrode 3 is patterned with theetched second interlayer insulating film 2 b used as a mask.

[0194] Referring to FIG. 115, first interlayer insulating film 2 a isetched for exposure of the bottom of the contact hole. At this time,second interlayer insulating film 2 b is etched simultaneously withetching of first interlayer insulating film 2 a (a portion shown by adotted line represents the etched second interlayer insulating film).Therefore, the thickness of second interlayer insulating film 2 b andthe thickness of first interlayer insulating film 2 a must satisfy thefollowing relation.

the thickness of second interlayer insulating film 2 b=the thickness ofthe finished second interlayer insulating film 2 b+the thickness offirst interlayer insulating film 2 a+α

[0195] In the above equation, +α is the amount of overetching forreliable exposure of the bottom of the contact hole.

[0196] By being thus structured, the thickness of second interlayerinsulating film 2 b will not become too small.

[0197] Embodiment 2

[0198] (Embodiment 2A)

[0199] FIGS. 14 to 21 are partial cross sectional views of asemiconductor device in respective steps in order of another method ofmanufacturing the contact hole transistor shown in FIG. 2.

[0200] Referring to FIG. 14, a silicon nitride film 12 of a thickness of500 Å is deposited on n⁻ type substrate 1.

[0201] Referring to FIGS. 14 and 15, silicon nitride film 12 ispatterned into a predetermined shape.

[0202] Referring to FIGS. 15 and 16, a portion not covered with siliconnitride film 12 is oxidized to form an isolation oxide film 13 on themain surface of substrate 1.

[0203] Referring to FIG. 17, impurities are implanted into the mainsurface of substrate 1 through silicon nitride film 12 to form a sourceregion 6.

[0204] Referring to FIG. 18, first interlayer insulating when siliconnitride film 12 is selectively removed to expose the surface substrate1, damage to substrate 1 can be minimized. As a result, when the contacthole is filled with amorphous silicon, and the amorphous silicon isgrown in a solid state, it is possible to grow a crystal having fewerdefects than the case of the method shown in Embodiment 1. By carryingout the process similar to that shown in FIGS. 10 to 12, a contact holetransistor is completed.

[0205] (Embodiment 2B)

[0206] This embodiment is another manner of Embodiment 2A.

[0207] In Embodiment 2A, referring to FIG. 116, in patterning firstinterlayer insulating film 2 a, gate electrode 3, and second interlayerinsulating film 2 b, three layers of second interlayer insulating film 2b, gate electrode 3, and first interlayer insulating film 2 a aresequentially etched with resist pattern 120 used as a mask. In etchingrespective layers, resist pattern 120 is also etched gradually. In thefigure, 120 h is a portion which is etched at the time of etching ofsecond interlayer insulating film 2 b, 120 i is a portion which isetched at the time of etching of gate electrode 3, and 120 j is aportion which is etched at the time of etching of first interlayerinsulating film 2 a. Therefore, when first interlayer insulating film 2a is finally etched, resist pattern 120 is very small in thickness.Therefore, resist pattern 120 is completely etched because of unstablefactors such as variation of etching and variation of the thickness ofresist, causing second interlayer insulating film 2 b which should notbe etched to be etched.

[0208] Embodiment 2B is for eliminating the above-described problem.

[0209] The process shown in FIGS. 14 to 17 is first carried out.

[0210] Referring to FIG. 117, gate electrode 3 is formed on firstinterlayer insulating film 2 a.

[0211] Referring to FIG. 118, resist pattern 120 having opening 120 a ata predetermined position is formed on gate electrode 3. Gate electrode 3is etched with resist pattern 120 used as a mask. Then, resist pattern120 is removed.

[0212] Referring to FIGS. 119 and 120, with gate electrode 3 used as amask, first interlayer insulating film 2 a is etched to expose thesurface of silicon nitride film 12.

[0213] Referring to FIG. 121, by annealing in the oxidizing atmosphere(O₂ or water vapor), the surface of gate electrode 3 is oxidized forformation of gate insulating film 4 and second interlayer insulatingfilm 2 b.

[0214] Referring to FIG. 122, silicon nitride film 12 at the bottomportion of the contact hole is removed by hot phosphorus.

[0215] The similar process as that shown in FIGS. 10 to 12 is carriedout to complete the semiconductor device.

[0216] Embodiment 3

[0217] This embodiment relates to a further method of manufacturing thecontact hole transistor shown in FIG. 2. FIGS. 22 to 27 are partialcross sectional views of a semiconductor device in respective steps inorder of the manufacturing method thereof.

[0218] Referring to FIG. 22, a source drawing-out electrode 41 fordrawing out a source electrode to an external terminal is formed onsubstrate (silicon substrate) 1 by ion implantation and heat treatmentcarried out thereafter. Source drawing-out electrode 41 has aconductivity type the same as that of a source region to be describedlater.

[0219] Referring to FIG. 23, a first interlayer insulating film 42, gateelectrode 3 of poly-crystalline silicon, and a second interlayerinsulating film 43 are sequentially deposited on substrate 1. Then,contact hole 19 penetrating through first interlayer insulating film 42,gate electrode 3, and second interlayer insulating film 43 is formed byreactive ion etching by a photolithography process.

[0220] Referring to FIG. 24, gate insulating film 4 covering an innerwill surface of contact hole 19 is formed with, for example, a CVDmethod.

[0221] Referring to FIG. 25, gate insulating film 4 is selectivelyetched by using anisotropic properties of reactive ion etching to leavegate insulating film 4 only on the sidewall of contact hole 19.

[0222] Substrate 1 is heat-treated at a temperature of approximately900° C. under reduced pressure in hydrogen. By this heat treatment, anatural oxide film grown in the surface of substrate 1 is reduced,sublimated and removed to expose a clean surface of substrate 1.

[0223] Referring to FIG. 26, an epitaxial Si layer 44 is grown on theclean surface of substrate 1 with a CVD method (900° C., 80 Torr) usingdichlorosilane. At this time, a source region 46 is first formed byintroduction of n-type impurities such as phosphorus, then a channelregion 45 is formed by introduction of p-type impurities such as boron,and then a drain region 47 is formed by introduction of n-typeimpurities to constitute a vertical type MOS transistor.

[0224] Referring to FIG. 27, a drain drawing-out region 48 for drawingout drain region 47 of the vertical type MOS transistor outside isformed on drain region 47. Then, by carrying out the process similar tothat shown in FIG. 12, the contact hole transistor as shown in FIG. 2 iscompleted.

[0225] The film thickness of epitaxial layer 44 will now be described.

[0226] The film thicknesses of source region 46 and drain region 47correspond to the film thicknesses of first interlayer insulating film42 and second interlayer insulating film 43, respectively. Firstinterlayer insulating film 42 must have a thickness large enough towithstand the voltage difference between gate and source. Secondinterlayer insulating film 43 must have a thickness large enough towithstand the voltage difference between gate and drain. For example,when a drive voltage is 5V, if an insulation breakdown voltage of theinterlayer insulating film is 7 MV/cm, the film thickness ofapproximately 700 Å or more is required. Therefore, the thickness ofsource region 46 and drain region 47 must be 700 Å or more. Thethickness of channel region 45 must be large enough to withstand anecessary breakdown voltage between source and drain. For example, whena drive voltage is 5V, approximately 0.6 μm or more is required.Therefore, as a conclusion, the thickness of epitaxial layer 44 must beapproximately 0.8 μm or more.

[0227] A further detailed description will now be given of a method offorming source region 46, channel region 45, and drain region 47.

[0228] Source region 16 is formed by epitaxial growth at a temperatureof 900° C. at a vacuum level of 80 Torr for 1 to 10 minutes by using amixed gas of PH₃ gas added to SiH₂Cl₂ gas and H₂ gas. The amount of PH₃gas is adjusted so that the phosphorus concentration of the epitaxiallygrown silicon layer is 10²⁰ to 10²² atomscm⁻³.

[0229] Channel region 45 is formed by epitaxial growth under the samecondition as described above by using a mixed gas of B₂H₆ gas added toSiH₂Cl₂ gas and H₂ gas. The amount of addition of B₂H₆ gas is adjustedso that the boron concentration is 10¹⁵ to 10 ⁷ atomscm⁻³.

[0230] Drain region 47 is formed with a method similar to that of sourceregion 46. Times required for epitaxial growth are 1 to 10 minutes (46),10 to 100 minutes (45), and 1 to 10 minutes (47), respectively.

[0231] Drain drawing-out region 48 shown in FIG. 27 is formed bydepositing a phosphorus doped polysilicon film up to a thickness of 1000Å with a low pressure CVD method at a temperature of 500° C. to 700° C.to pattern the polysilicon film by photolithography and etching.

[0232] According to this embodiment, since the channel region is formedby epitaxial growth, crystal properties of the channel region isimproved, which in turn improving the transistor characteristic. Sinceconductivity types of the semiconductor can be changed only by changinggas at the time of growth of layer 44, the process can be simplified.

[0233] Embodiment 4

[0234] This embodiment is a further improvement of the contact holetransistor shown in FIG. 2.

[0235]FIG. 28 is a cross sectional view of a contact hole transistoraccording to Embodiment 4. First impurity diffusion layer 6 a serving asone source/drain region is provided in the main surface of substrate 1.First interlayer insulating film 2 a is provided on substrate 1. Gateelectrode 3 is provided on first interlayer insulating film 2 a. Secondinterlayer insulating film 2 b is provided on first interlayerinsulating film 2 a so as to cover gate electrode 3. Contact hole 19 forexposing a part of the surface of first impurity diffusion layer 6 a isprovided so as to penetrate through first interlayer insulating film 2a, gate electrode 3, and second interlayer insulating film 2 b. Asidewall surface of contact hole 19 is covered with gate insulating film4. The transistor includes a silicon thin film 39 having a recessedportion in contact hole 19, provided in contact with first impuritydiffusion layer 6 a and covering continuously the sidewall surface ofcontact hole 19 with gate insulating film 4 interposed therebetween. Aninsulating film 30 is provided on substrate 1 so as to fill the recessedportion of silicon thin film 39. Silicon thin film 39 is divided intothree portions of cylindrical channel region 7 positioned at a portionsurrounded by gate electrode 3, a source region 6 aa and drain region 6b sandwiching channel region 7 from upper and lower sides. The thicknessof silicon thin film 39 in channel region 7 is equal to or less than themaximum depletion layer width.

[0236] In the contact hole transistor according to Embodiment 1, thatis, shown in FIG. 2, when the radius of contact hole 19 is 0.3 μm ormore, for example, the radius of channel portion 7 of the transistorbecomes too large, making it difficult to completely deplete channelportion 7 when the transistor is turned on. When an N channel transistoris considered, for example, the depletion layer extends from the outerside surface of cylindrical channel portion 7 as the gate voltagechanges from negative to positive. Since the radius of channel portion 7is large, an inversion layer is formed on the outer side surface ofchannel portion 7 before channel portion 7 has been completely depleted.More specifically, the transistor is operated in a state where channelportion 7 is not completely depleted. Therefore, the originalcharacteristic is lost that the threshold coefficient is small.

[0237] On the other hand, in Embodiment 4, transistor 8 is formed bydepositing thin silicon film 39 (for example, 100 Å) covering an innerwall surface of contact hole 19. Since channel portion 7 is small inthickness, complete depletion of channel portion 7 is easily achieved.More specifically, as the gate voltage changes from negative topositive, a depletion layer extends inwardly from the outer surface ofchannel portion 7. At this time, since the thickness of channel portion7 is small, the depletion layer reaches insulating film 30 at a portionwhere the gate voltage is low. In this state, depletion layercapacitance Cd of the channel becomes identical to a capacitance of acapacitance of the depleted silicon film and a capacitance of insulatingfilm 30 which are series-coupled to each other, which in turn rapidlydecreases depletion layer capacitance Cd of the channel. Since thesubthreshold coefficient becomes small as depletion layer capacitance Cddecreases, the subthreshold coefficient rapidly becomes small at thetime when the depletion layer reaches insulating film 30.

[0238] A drain current (off current) in the off state of the transistoris proportional to a junction area of the drain. The junction area ofthe drain is made smaller in a structure in which the sidewall surfaceof contact hole 19 is covered with a silicon thin film than in astructure in which contact hole 19 has a channel portion therein (oneshown in FIG. 2), which in turn decreases the off current more.

[0239] Embodiment 5

[0240] This embodiment relates to a method of manufacturing the contacthole transistor shown in FIG. 28. First, the process identical to thatshown in FIGS. 4 to 9, which was described regarding to Embodiment 1, iscarried out.

[0241] Referring to FIG. 29(a), amorphous silicon film 5 of 100 Å isdeposited on substrate 1 so as to cover the inner wall surface ofcontact hole 19.

[0242] Referring to FIG. 29(b), arsenic ions 31 are rotationallyimplanted into the surface of amorphous silicon film 5 at a tilt angleof θ. The implantation conditions are, for example, implantation energyof 10 keV, and a concentration of 5×10¹⁵ atoms/cm².

[0243] Let a dimension in the vertical direction of a portion into whicharsenic ions are implanted be S, and the diameter of contact hole 19 be2R, the following expression holds:

tan θ=S/2R

[0244] By determining θ, the dimension S in the vertical direction ofthe portion (6 b) into which arsenic ions are implanted is determined.

[0245] Then, heat treatment is carried out to cause heat diffusion ofimpurity ions. More specifically, implanted arsenic diffuses in thevertical direction in amorphus silicon film 5, and diffuses from sourceregion 6 a into amorphous silicon film 5, causing source region 6 a anddrain region 6 b to approach gate electrode 3.

[0246] Then, a silicon oxide film having a thickness of 3000 Å isdeposited in contact hole 19 with a CVD method, whereby the contact holetransistor shown in FIG. 28 is completed.

[0247] Embodiment 6

[0248] This embodiment relates to another method of manufacturing thecontact hole transistor shown in FIG. 28.

[0249] FIGS. 30 to 32 are partial cross sectional views of asemiconductor device in respective main steps of the manufacturingmethod according to Embodiment 6.

[0250] In this embodiment, similar to the case of Embodiment 5, theprocess up to the step shown in FIG. 29 is first carried out.

[0251] Referring to FIG. 30, a silicon oxide film 32 of a thickness of500 Å is deposited on amorphus silicon film 5 with a CVD method.

[0252] Referring to FIG. 31, silicon oxide film 32 is anisotropicallyetched so that silicon oxide film 32 is

What is claimed is:
 1. A semiconductor device controlling a flow ofmajority carriers by a voltage applied to a gate, comprising: asubstrate having a main surface; a first conductive layer of a firstconductivity type provided in the main surface of said substrate andserving as one source/drain region; a first interlayer insulating filmprovided on said substrate; a gate electrode provided on said firstinterlayer insulating film and having an upper surface and a lowersurface; a second interlayer insulating film provided on said firstinterlayer insulating film so as to cover said gate electrode; a contacthole provided so as to penetrate through said first interlayerinsulating film, said gate electrode, and said second interlayerinsulating film for exposing a part of the surface of said firstconductive layer; a gate insulating film covering a sidewall surface ofsaid contact hole; a first semiconductor layer of a first conductivitytype formed on the surface of said first conductive layer in contacttherewith up to the lower surface of said gate electrode in said contacthole; a channel semiconductor layer formed on the surface of said firstsemiconductor layer in contact therewith up to the upper surface of saidgate electrode in said contact hole; and a second semiconductor layer ofa first conductivity type provided on said channel semiconductor layerin contact with the surface of said channel semiconductor layer andserving as the other source/drain region.
 2. The semiconductor device asrecited in claim 1, wherein said channel semiconductor layer is acylinder extending upward in a direction perpendicular with respect tosaid substrate, and the radius of said cylinder is at most the maximumdepletion layer width.
 3. The semiconductor device as recited in claim1, wherein said channel semiconductor layer is a polygonal cylinderextending upward in a direction perpendicular with respect to saidsemiconductor substrate and having a cross section of a polygon, and theradius of the largest inscribed circle inscribing said polygon is atmost the maximum depletion layer width.
 4. The semiconductor device asrecited in claim 1, comprising: a third interlayer insulating filmprovided on said substrate so as to cover said second semiconductorlayer; a connection hole provided in said third interlayer insulatingfilm for exposing a part of the surface of said second semiconductorlayer; and an electrode connected to said second conductive layerthrough said connection hole, wherein the diameter of said channelsemiconductor layer is at most the diameter of said connection hole. 5.A semiconductor device controlling a flow of majority carriers by avoltage applied to a gate, comprising: a substrate having a mainsurface; a first conductive layer of a first conductivity type providedin the main surface of said substrate and serving as one source/drainregion; a first interlayer insulating film provided on said substrate; agate electrode provided on said first interlayer insulating film andhaving an upper surface and a lower surface; a second interlayerinsulating film provided on said first interlayer insulating film so asto cover said gate electrode; a contact hole provided so as to penetratethrough said first interlayer insulating film, said gate electrode, andsaid second interlayer insulating film for exposing a part of thesurface of said first conductive layer; a gate insulating film coveringa sidewall surface of said contact hole; a silicon thin film provided incontact with said first conductive layer covering continuously asidewall surface of said contact hole with said gate insulating filminterposed therebetween and having a recessed portion in a portion ofthe contact hole; and an insulating film provided on said substrate tofill the recessed portion of said silicon thin film, wherein saidsilicon thin film is divided into three portions of a cylindricalchannel portion positioned in a portion surrounded by said gateelectrode, and a source region and a drain region sandwiching saidchannel portion from opposite sides, and the thickness of said siliconthin film in said channel portion is at most the maximum depletion layerwidth.
 6. The semiconductor device as recited in claim 5, wherein anupper end surface of said channel portion is made higher than the uppersurface of said gate electrode.
 7. A semiconductor device controlling aflow of majority carriers by a voltage applied to a gate, comprising: asubstrate having a main surface; a first conductive layer of a firstconductivity type provided in the main surface of said substrate andserving as one source/drain region; a first interlayer insulating filmprovided on said substrate; a first gate electrode provided on saidfirst interlayer insulating film and having an upper surface and a lowersurface; a second interlayer insulating film provided on said firstinterlayer insulating film so as to cover said first gate electrode; acontact hole provided so as to penetrate through said first interlayerinsulating film, said first gate electrode, and said second interlayerinsulating film for exposing a part of the surface of said firstconductive layer; a first gate insulating film covering a sidewallsurface of said contact hole; and a silicon thin film provided incontact with said first conductive layer covering continuously an innerwall surface of said contact hole with said first gate insulating filminterposed therebetween, and having a recessed portion having a bottomsurface positioned at or lower than the lower surface of said first gateelectrode in said contact hole, wherein said silicon thin film isdivided into three portions of a cylindrical channel portion positionedin a portion surrounded by said first gate electrode, and a sourceregion and a drain region sandwiching said channel portion from oppositesides, and the thickness of said silicon thin film in said channelportion is at most double of the maximum depletion layer width, saidsemiconductor device further comprising: a second gate insulating filmprovided on said substrate so as to cover said recessed portion of saidsilicon thin film; and a second gate electrode filling said recessedportion of said silicon thin film and opposing said channel portion withsaid second gate insulating film interposed therebetween.
 8. Asemiconductor device storing information using a gate transistor in acapacitor provided at a crossing point of a bit line and a word line,and formed of a storage node, a capacitor insulating film, and a cellplate electrode, comprising: a substrate having a main surface; a firstimpurity diffusion layer of a first conductivity type provided in themain surface of said substrate, having impurity of a first conductivitytype implanted therein, and serving as one source/drain region and alsoas said bit line; a first interlayer insulating film provided on saidsubstrate; a gate electrode provided on said first interlayer insulatingfilm and having an upper surface and a lower surface; a secondinterlayer insulating film provided on said first interlayer insulatingfilm so as to cover said gate electrode; a contact hole provided so asto penetrate through said first interlayer insulating film, said gateelectrode, and said second interlayer insulating film for exposing apart of the surface of said first impurity diffusion layer; a gateinsulating film covering a sidewall surface of said contact hole; afirst semiconductor layer of a first conductivity type formed on thesurface of said first impurity diffusion layer in contact therewith upto the lower surface of said gate electrode in said contact hole; achannel semiconductor layer formed on the surface of said firstsemiconductor layer in contact therewith up to the upper surface of saidgate electrode in said contact hole; a second conductive layer of afirst conductivity type provided on said channel semiconductor layer incontact therewith and serving as the other source/drain region and alsoas said storage node; a capacitor insulating film provided on saidsecond conductive layer; and a cell plate electrode provided on saidstorage node with said capacitor insulating film interposedtherebetween.
 9. A semiconductor device storing information using a gatetransistor in a capacitor provided at a crossing point of a bit line anda word line, and formed of a storage node, a capacitor insulating film,and a cell plate electrode, comprising: a substrate having a mainsurface; a first conductive layer of a first conductivity type providedin the main surface of said substrate and serving as one source/drainregion; a first interlayer insulating film provided on said substrate; agate electrode provided on said first interlayer insulating film andhaving an upper surface and a lower surface; a second interlayerinsulating film provided on said first interlayer insulating film so asto cover said gate electrode; a contact hole provided so as to penetratethrough said first interlayer insulating film, said gate electrode, andsaid second interlayer insulating film for exposing a part of thesurface of said first conductive layer; a gate insulating film coveringa sidewall surface of said contact hole; and a silicon thin filmprovided in contact with said first conductive layer coveringcontinuously the sidewall surface of said contact hole with said gateinsulating film interposed therebetween, and having a recessed portionhaving a bottom surface positioned at or lower than the lower surface ofsaid gate electrode in said contact hole, wherein said silicon thin filmis divided into three portions of a cylindrical channel portionpositioned in a portion surrounded by said gate electrode, onesource/drain region positioned at the lower side and the othersource/drain region positioned at the upper side, sandwiching saidchannel portion from opposite sides, the thickness of said silicon thinfilm in said channel portion is at most the maximum deletion layerwidth, and said the other source/drain region is used also as a storagenode, said semiconductor device further comprising: a capacitorinsulating film provided on said substrate so as to cover said recessedportion of said silicon thin film; and a cell plate electrode providedon said substrate so as to cover said silicon thin film with saidcapacitor insulating film interposed therebetween and to fill therecessed portion of said silicon thin film.
 10. The semiconductor deviceas recited in claim 9, wherein the lowermost end of said cell plateelectrode is positioned at least the upper surface of said gateelectrode in said recessed portion.
 11. A semiconductor device storinginformation using a gate transistor in a capacitor provided at acrossing point of a bit line and a word line, and formed of a storagenode, a capacitor insulating film, and a cell plate electrode,comprising: a substrate having a main surface; a first conductive layerof a first conductivity type provided in the main surface of saidsubstrate and serving as one source/drain region; a first interlayerinsulating film provided on said substrate; a gate electrode provided onsaid first interlayer insulating film and having an upper surface and alower surface; a second interlayer insulating film provided on saidfirst interlayer insulating film so as to cover said gate electrode; afirst contact hole provided so as to penetrate through said firstinterlayer insulating film, said gate electrode, and said secondinterlayer insulating film for exposing a part of the surface of saidfirst conductive layer; a gate insulating film covering a sidewallsurface of said first contact hole; and a silicon thin film provided incontact with said first conductive layer covering continuously an innerwall surface of said first contact hole with said gate insulating filminterposed therebetween, and having a recessed portion having a bottomsurface positioned at or lower than the lower surface of said gateelectrode in said first contact hole, wherein said silicon thin film isdivided into three portions of a cylindrical channel portion positionedin a portion surrounded by said gate electrode, one source/drain regionpositioned at the lower side and the other source/drain regionpositioned at the upper side sandwiching said channel portion fromopposite sides, and the thickness of said silicon thin film in saidchannel portion is at most the maximum depletion layer width, saidsemiconductor device further comprising: a third interlayer insulatingfilm provided on said substrate so as to cover said silicon thin film; asecond contact hole provided in said third interlayer insulating filmfor exposing a part of the surface of said the other source/drainregion; a storage node provided in contact with said the othersource/drain region and covering an inner wall surface of said secondcontact hole; a capacitor insulating film provided on said substrate soas to cover the surface of said storage node; and a cell plate electrodeprovided on said substrate so as to oppose said storage node with saidcapacitor insulating film interposed therebetween and to fill saidsecond contact hole.
 12. A semiconductor device inverting logics of aninput signal and an output signal, comprising: a substrate; a conductivelayer provided on said substrate; a first interlayer insulating filmprovided on said substrate so as to cover said conductive layer; a gateelectrode provided on said first interlayer insulating film and havingan upper surface and a lower surface; a second interlayer insulatingfilm provided on said substrate so as to cover said gate electrode; afirst contact hole provided so as to penetrate through said firstinterlayer insulating film, said gate electrode, and said secondinterlayer insulating film for exposing one part of the surface of saidconductive layer; a second contact hole provided so as to penetratethrough said first interlayer insulating film, said gate electrode, andsaid second interlayer insulating film for exposing another part of thesurface of said conductive layer; a gate insulating film covering aninner wall surface of said first contact hole; a gate insulating filmcovering an inner wall surface of said second contact hole; a first p⁺semiconductor layer formed on the surface of said conductive layer incontact with said one part thereof up to the lower surface of said gateelectrode in said first contact hole, and serving as one source/drainregion; an n⁻ semiconductor layer formed on the surface of said p⁺semiconductor layer in contact therewith up to the upper surface of saidgate electrode in said first contact hole; a second p⁺ semiconductorlayer provided on said n⁻ semiconductor layer in contact with thesurface of said n⁻ semiconductor layer and serving as the othersource/drain region; a first n⁺ semiconductor layer formed on thesurface of said conductive layer in contact with said another partthereof up to the lower surface of said gate electrode in said secondcontact hole and serving as the other source/drain region; a p⁻semiconductor layer formed on the surface of said first n⁺ semiconductorlayer in contact therewith up to the upper surface of said gateelectrode in said second contact hole; and a second n⁺ semiconductorlayer provided on said p⁻ semiconductor layer in contact therewith andserving as the other source/drain region.
 13. A semiconductor deviceinverting logics of an input signal and an output signal, comprising: asemiconductor substrate having a main surface; a field oxide film formedin the main surface of said semiconductor substrate; an n⁺ impuritydiffusion layer provided in the main surface of said semiconductorsubstrate and directly under said field oxide film; a gate electrodeprovided on said field oxide film and having an upper surface and alower surface; an interlayer insulating film provided on saidsemiconductor substrate so as to cover said gate electrode; a firstcontact hole provided so as to penetrate through said interlayerinsulating film, said gate electrode, and said field oxide film forexposing one part of the surface of said n⁺ impurity diffusion layer; asecond contact hole provided so as to penetrate through said interlayerinsulating film, said gate electrode, and said field oxide film forexposing another part of the surface of said n⁺ impurity diffusionlayer; a gate insulating film covering an inner wall surface of saidfirst contact hole; a gate insulating film covering an inner wallsurface of said second contact hole; a conductor film provided incontact with said one part of said n⁺ impurity diffusion layer in saidfirst contact hole; a first p⁺ semiconductor layer formed on the surfaceof said conductor film in contact therewith up to the lower surface ofsaid gate electrode in said first contact hole and serving as onesource/drain region; an n⁻ semiconductor layer formed on the surface ofsaid first p⁺ semiconductor layer in contact therewith up to the uppersurface of said gate electrode in said first contact hole; a second p⁺semiconductor layer provided on said n⁻ semiconductor layer in contacttherewith and serving as the other source/drain region; a first n⁺semiconductor layer formed on the surface of said n⁺ impurity diffusionlayer in contact with said another part thereof up to the lower surfaceof said gate electrode in said second contact hole and serving as onesource/drain region; a p⁻ semiconductor layer formed on the surface ofsaid first n⁺ semiconductor layer in contact therewith up to the uppersurface of said gate electrode in said second contact hole; and a secondn⁺ semiconductor layer provided on said p⁻ semiconductor layer incontact therewith and serving as the other source/drain region.
 14. Asemiconductor device inverting logics of an input signal and an outputsignal, comprising: a semiconductor substrate having a main surface; afield oxide film formed in the main surface of said semiconductorsubstrate; a p⁺ impurity diffusion layer and an n⁺ impurity diffusionlayer formed in the main surface of said semiconductor substrateseparately from each other by said field oxide film; a first interlayerinsulating film provided on said semiconductor substrate; a gateelectrode provided on said first interlayer insulating film so as tocover said p⁺ impurity diffusion layer and said n⁺ impurity diffusionlayer; a second interlayer insulating film provided on saidsemiconductor substrate so as to cover said gate electrode; a firstcontact hole provided so as to penetrate through said first interlayerinsulating film, said gate electrode, and said second interlayerinsulating film for exposing a part of the surface of said p⁺ impuritydiffusion layer; a second contact hole provided so as to penetratethrough said first interlayer insulating film, said gate electrode, andsaid second interlayer insulating film for exposing a part of thesurface of said n⁺ impurity diffusion layer; a gate insulating filmcovering an inner wall surface of said first contact hole; a gateinsulating film covering an inner wall surface of said second contacthole; a first p⁺ semiconductor layer formed on the surface of said p⁺impurity diffusion layer in contact therewith up to the lower surface ofsaid gate electrode in said first contact hole and serving as onesource/drain region; an n⁻ semiconductor layer formed on the surface ofsaid first p⁺ semiconductor layer in contact therewith up to the uppersurface of said gate electrode in said first contact hole; a second p⁺semiconductor layer provided on said n⁻ semiconductor layer and servingas the other source/drain region; a first n⁺ semiconductor layer formedon the surface of said n⁺ impurity diffusion layer in contact therewithup to the lower surface of said gate electrode in said second contacthole and serving as one source/drain region; a p⁻ semiconductor layerformed on the surface of said first n⁺ semiconductor layer in contacttherewith up to the upper surface of said gate electrode in said secondcontact hole; and a second n⁺ semiconductor layer provided on said p⁻semiconductor layer in contact therewith and serving as the othersource/drain region, wherein an end portion of said second p⁺semiconductor layer and an end portion of said second n⁺ semiconductorlayer are in contact with each other on said field oxide film, thesemiconductor device further comprising a connection member electricallyconnecting the surface of said second p⁺ semiconductor layer and thesurface of said second n⁺ semiconductor layer.
 15. A semiconductordevice serving as a logic circuit in a cooperative operation of a firsttransistor and a second transistor, comprising: a substrate; an SiO₂layer provided on said substrate; a semiconductor layer provided on saidSiO₂ layer and having an upper surface and a lower surface; a gateelectrode of said first transistor provided on said semiconductor layerwith an insulating film interposed therebetween; a pair of source/drainregions of said first transistor provided in said semiconductor layerseparately from each other on both sides of said gate electrode; acontact hole provided at a position spaced from the gate electrode ofsaid first transistor so as to penetrate through said insulating film,one of said source/drain regions, and said SiO₂ layer for exposing apart of the surface of said substrate; a gate insulating film for saidsecond transistor covering an inner wall surface of said contact hole;one source/drain layer of said second transistor formed on the surfaceof said substrate in contact therewith up to the lower surface of saidsemiconductor layer in said contact hole; a channel layer of said secondtransistor formed on the surface of one source/drain layer of saidsecond transistor in contact therewith up to the upper surface of saidsemiconductor layer in said contact hole; and the other source/drainlayer of said second transistor provided on the channel layer of saidsecond transistor in contact therewith.
 16. A semiconductor deviceinverting logics of an input signal and an output signal in acooperative operation of a first transistor and a second transistor,comprising: a substrate; a first insulating film provided on saidsubstrate; a gate electrode of said first transistor provided on saidfirst insulating film and having an upper surface and a lower surface; asecond insulating film provided on said substrate so as to cover thegate electrode of said first transistor; a contact hole provided so asto penetrate through the gate electrode of said first transistor andsaid second insulating film for exposing a part of the surface of saidsubstrate; one source/drain layer of said second transistor provided inthe main surface of said substrate and directly below said contact hole;a gate insulating film of said second transistor covering an inner wallsurface of said contact hole; a channel layer of said second transistorformed on the surface said one source/drain layer of said secondtransistor in contact therewith up to the upper surface of said gateelectrode in said contact hole; and the other source/drain layer of saidsecond transistor provided on the channel layer of said secondtransistor in contact therewith.
 17. A semiconductor device storinginformation in a cooperative operation of four transistors, comprising:a flip-flop formed of two inverter circuits defined in claim 14; and twotransistors.
 18. A semiconductor device storing information in acooperative operation of four transistors, characterized in that atransistor defined in claim 1 is used as an access transistor.
 19. Asemiconductor device storing information in a cooperative operation offour transistors, characterized in that an access transistor and a loadtransistor are respectively formed of a transistor defined in claim 1.20. A method of manufacturing a semiconductor device controlling a flowof majority carriers by a voltage applied to a gate, comprising thesteps of: forming in a main surface of a substrate a first conductivelayer including impurity of a first conductivity type serving as onesource/drain region; forming a first interlayer insulating film on saidsubstrate; forming a gate electrode having an upper surface and a lowersurface on said first interlayer insulating film; forming a secondinterlayer insulating film on said substrate so as to cover said gateelectrode; forming a contact hole penetrating through said firstinterlayer insulating film, said gate electrode, and said secondinterlayer insulating film into the surface of said first conductivelayer; covering a sidewall surface of said contact hole with a gateinsulating film; forming a semiconductor layer on said substrate incontact with the surface of said first conductive layer so as to fillsaid contact hole; implanting impurity of a first conductivity type intothe surface of said semiconductor layer; and diffusing said impurityimplanted into the surface of said semiconductor layer in saidsemiconductor layer, and diffusing said impurity included in said firstconductive layer from said first conductive layer to said semiconductorlayer, thereby forming in said semiconductor layer the othersource/drain region and a channel region sandwiched by said the othersource/drain region and said one source/drain region.
 21. A method ofmanufacturing a semiconductor device controlling a flow of majoritycarriers by a voltage applied to a gate, comprising the steps of:forming a silicon nitride film on a main surface of a substrate;implanting impurity into the main surface of said substrate through saidsilicon nitride film and forming in the main surface of said substrate afirst conductive layer including impurity of a first conductivity typeserving as one source/drain region; forming a first interlayerinsulating film on said substrate so as to cover said silicon nitridefilm; forming a gate electrode having an upper surface and a lowersurface on said first interlayer insulating film; forming a secondinterlayer insulating film on said substrate so as to cover said gateelectrode; forming a contact hole penetrating through said firstinterlayer insulating film, said gate electrode, and said secondinterlayer insulating film into the surface of said silicon nitridefilm; oxidizing a sidewall surface of said contact hole for forming agate insulating film; etching an exposed surface of said silicon nitridefilm for exposing the surface of said first conductive layer; forming asemiconductor layer on said substrate in contact with the exposedsurface of said first conductive layer and filling said contact hole;implanting impurity of a first conductivity type into the surface ofsaid semiconductor layer; and diffusing said impurity implanted into thesurface of said semiconductor layer in said semiconductor layer, anddiffusing said impurity included in said first conductive layer fromsaid first conductive layer to said semiconductor layer, thereby formingin the semiconductor layer the other source/drain region and a channelregion sandwiched by the other source/drain region and the onesource/drain region.
 22. The method of manufacturing a semiconductordevice as recited in claim 21, wherein the thickness of said secondinterlayer insulating film is larger than that of said first interlayerinsulating film.
 23. A method of manufacturing a semiconductor devicecontrolling a flow of majority carriers by a voltage applied to a gate,comprising the steps of: forming in a main surface of a substrate, afirst source/drain drawing-out electrode for drawing out a source/drainelectrode to an external terminal; sequentially forming a firstinterlayer insulating film, a gate electrode, and a second interlayerinsulating film on said substrate; forming a contact hole penetratingthrough said first interlayer insulating film, said gate electrode, andsaid second interlayer insulating film for exposing a part of thesurface of said first source/drain drawing-out electrode; covering aninner wall surface of said contact hole with a gate insulating film;sequentially forming in said contact hole, a first epitaxial siliconlayer including impurity of a first conductivity type, a secondepitaxial silicon layer including impurity of a second conductivitytype, and a third epitaxial silicon layer including impurity of a firstconductivity type; and forming a second source/drain drawing-outelectrode on said third epitaxial silicon layer.
 24. A method ofmanufacturing a semiconductor device controlling a flow of majoritycarriers by a voltage applied to a gate, comprising the steps of:forming in a main surface of a substrate a first conductive layerincluding impurity of a first conductivity type serving as onesource/drain region; forming a first interlayer insulating film on saidsubstrate; forming a gate electrode having an upper surface and a lowersurface on said first interlayer insulating film; forming a secondinterlayer insulating film on said substrate so as to cover said gateelectrode; forming a contact hole penetrating through said firstinterlayer insulating film, said gate electrode, and said secondinterlayer insulating film into the surface of said first conductivelayer; covering a sidewall surface of said contact hole with a gateinsulating film; forming a semiconductor film on said substrate so as tocover the surface of said first conductive layer and an inner wallsurface of said contact hole with said gate insulating film interposedtherebetween; implanting impurity of a first conductivity type into thesurface of said semiconductor film with a rotational ion implantationmethod; and diffusing said impurity implanted into the surface of saidsemiconductor film in said semiconductor film, and diffusing saidimpurity included in said first conductive layer from said firstconductive layer to said semiconductor film, thereby forming in saidsemiconductor film the other source/drain region and a channel regionsandwiched by said the other source/drain region and said onesource/drain region; and filling said contact hole with an insulatingfilm so as to be in contact with said semiconductor film.
 25. A methodof manufacturing a semiconductor device controlling a flow of majoritycarriers by a voltage applied to a gate, comprising the steps of:forming in a main surface of a substrate a first conductive layerincluding impurity of a first conductivity type serving as onesource/drain region; forming a first interlayer insulating film on saidsubstrate; forming a gate electrode having an upper surface and a lowersurface on said first interlayer insulating film; forming a secondinterlayer insulating film on said substrate so as to cover said gateelectrode; forming a contact hole penetrating through said firstinterlayer insulating film, said gate electrode, and said secondinterlayer insulating film into the surface of said first conductivelayer, covering a sidewall surface of said contact hole with a gateinsulating film; forming a semiconductor film on said substrate so as tocover the surface of said first conductive layer and an inner wallsurface of said contact hole; forming a first insulating film on asidewall surface of said contact hole with said semiconductor filminterposed therebetween; implanting impurity of a first conductivitytype into the surface of said semiconductor film in a directionperpendicular to said substrate with said first insulating film used asa mask; diffusing said impurity implanted into the surface of saidsemiconductor film in said semiconductor film, and diffusing saidimpurity including said first conductive layer from said firstconductive layer to said semiconductor film, thereby forming in saidsemiconductor film the other source/drain region and a channel regionsandwiched by said the other source/drain region and said onesource/drain region; and filling said contact hole with a secondinsulating film so as to be in contact with said first insulating filmand said semiconductor film.
 26. A method of manufacturing asemiconductor device controlling a flow of majority carriers by avoltage applied to a gate, comprising the steps of: forming in a mainsurface of a substrate a first conductive layer including impurity of afirst conductivity type serving as one source/drain region; forming afirst interlayer insulating film on said substrate; forming a gateelectrode having an upper surface and a lower surface on said firstinterlayer insulating film; forming a second interlayer insulating filmon said substrate so as to cover said gate electrode; forming a contacthole penetrating through said first interlayer insulating film, saidgate electrode, and said second interlayer insulating film into thesurface of said first conductive layer, covering a sidewall surface ofsaid contact hole with a gate insulating film; forming a semiconductorfilm on said substrate so as to cover the surface of said firstconductive layer and an inner wall surface of said contact hole; fillingsaid contact hole with an insulating film so as to be in contact withsaid semiconductor film; implanting impurity of a first conductivitytype into the surface of said semiconductor film; and diffusing saidimpurity implanted into the surface of said semiconductor film in saidsemiconductor film, and diffusing said impurity included in said firstconductive layer from said first conductive layer to said semiconductorfilm, thereby forming in said semiconductor film the other source/drainregion and a channel region sandwiched by said the other source/drainregion and said one source/drain region.
 27. A method of manufacturing asemiconductor device controlling a flow of majority carriers by avoltage applied to a gate, comprising the steps of: forming in a mainsurface of a substrate a first conductive layer including impurity of afirst conductivity type serving as one source/drain region; forming afirst interlayer insulating film on said substrate; forming a first gateelectrode having an upper surface and a lower surface on said firstinterlayer insulating film; forming a second interlayer insulating filmon said substrate so as to cover said gate electrode; forming a contacthole penetrating through said first interlayer insulating film, saidfirst gate electrode, and said second interlayer insulating film intothe surface of said conductive layer; covering a sidewall surface ofsaid contact hole with a first gate insulating film; forming asemiconductor film in contact with the surface of said first conductivelayer so as to cover an inner wall surface of said contact hole withsaid first gate insulating film interposed therebetween; forming in saidsemiconductor film one source/drain region connected to said firstconductive layer, a channel region connected to said one source/drainregion, and the other source/drain region connected to said channelregion; forming on said substrate a second gate insulating film coveringan inner wall surface of said contact hole with said semiconductor filminterposed therebetween; and filling a second gate electrode in saidcontact hole so as to oppose said semiconductor film with said secondgate insulating film interposed therebetween.
 28. A method ofmanufacturing a semiconductor device controlling a flow of majoritycarriers by a voltage applied to a gate, comprising the steps of:forming in a main surface of a substrate a first conductive layerincluding impurity of a first conductivity type serving as onesource/drain region; forming a first interlayer insulating film on saidsubstrate; forming a gate electrode having an upper surface and a lowersurface on said first interlayer insulating film; forming a secondinterlayer insulating film on said substrate so as to cover said gateelectrode; forming a contact hole penetrating through said firstinterlayer insulating film, said gate electrode, and said secondinterlayer insulating film into the surface of said first conductivelayer; covering a sidewall surface of said contact hole with a gateinsulating film; forming a semiconductor layer on said substrate so asfill said contact hole; forming in said semiconductor layer onesource/drain region of a first conductivity type in contact with saidfirst conductive layer; forming in said semiconductor layer a channelregion of a second conductivity type connected to said one source/drainregion; forming in said semiconductor layer a region of a lowconcentration of the other source/drain region of a first conductivitytype connected to said channel region; and forming in semiconductorlayer a region of a high concentration of the other source/drain regionof a first conductivity type connected to said region of a lowconcentration.
 29. A semiconductor device storing information using agate transistor in a capacitor provided at a crossing point of a bitline and a word line, and formed of a storage node, a capacitorinsulating film, and a cell plate electrode, comprising: a substrate; acell plate electrode provided on said substrate; a storage node providedon said substrate so as to cover said cell plate electrode with acapacitor insulating film interposed therebetween; one source/drainregion provided on said storage node; a transistor provided on said onesource drain region so as to be connected thereto; and the othersource/drain region provided on said transistor, wherein said transistorincludes a gate electrode having an upper surface and a lower surfaceand provided between said one source/drain region and said the othersource/drain region, a contact hole provided so as to penetrate throughsaid gate electrode and connecting said one source/drain region and saidthe other source/drain region, a gate insulating film covering an innerwall surface of said contact hole, and a channel semiconductor layerfilling said contact hole.